Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Sadatoshi Murakami

Ryota Katsumata

Tomoo Hishida

Masao Iwase

Fumiharu Nakajima

Weiting Wang

Yoko Yokoyama

Hiroomi Nakajima

Miki Toshima

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Semiconductor memory having memory cell regions and other regions alternately along a bit line direction

Semiconductor memory having memory cell regions and other regions alternately arranged along a bit line direction

Semiconductor memory having first and second memory cell regions separated by a third region along a bit line direction

According to one embodiment, a quality control method of a position measurement light source includes irradiating light of the position measurement light source on a plurality of marks having different heights and measuring a relationship between the height of the mark and an intensity of light reflected by the mark. The quality control method includes identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.

Quality control method of position measurement light source, semiconductor manufacturing apparatus, and method for manufacturing semiconductor device

Semiconductor memory

According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.

Semiconductor device and method of manufacturing the semiconductor device

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers and a first step portion, the first step portion having the plurality of electrode layers provided stepwise; a column provided in a region of the stacked body other than a region in the first step portion provided; and a plurality of insulating portions provided in the first step portion. The stacked body includes a metal silicide portion provided between the plurality of insulating portions and the plurality of electrode layers, a plurality of terraces provided on a top surface of each of the plurality of electrode layers of the first step portion, and a plurality of contact portions provided on the plurality of terraces.

Semiconductor memory device and method for manufacturing same

According to one embodiment, the underlying film includes a memory region including a first trench and a peripheral region including a second trench. The stacked body includes conductive layers and insulating layers alternately stacked on the underlying film. The channel body is provided in a pair of first holes and the first trench. The first holes pierce the stacked body to be connected to the first trench. The memory film includes a charge storage film provided between a side wall of the first hole and the channel body, and between an inner wall of the first trench and the channel body. The conductor is provided in a pair of second holes and the second trench. The second holes pierce the stacked body to be connected to the second trench.

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of pillars and a plurality of sidewall films on a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers. The pillars are arranged in a first direction and a second direction intersecting the first direction at different pitches in the first direction and the second direction. The sidewall films are provided on outer circumferential surfaces of the pillars to extend in the first direction to be linked in the first direction and separated in the second direction. The method includes making a slit to divide the stacked body in the second direction by etching the stacked body under a region between the sidewall films adjacent to each other in the second direction using the pillars and the sidewall films as a mask.

Growing community of inventors

Yokohama Kanagawa, Japan

Sadatoshi Murakami