Oracle International Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Intergraph Corporation

Sadar U Ahmed

Robert Paul Masleid

Jeffrey S Brooks

The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.

Efficient silent code assignment to a set of logical codes

A method for determining a mapping between two code spaces is disclosed. The method may include receiving first and second plurality of data words. The least-significant-bits (LSBs) of a first data word of a first subset of the first plurality of data words may be compared to the LSBs of each data word of a second subset of the second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.

An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.

Variable run length encoding of a bit stream

A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count and output an aligned addend, a multiplier configured to multiply a first multiplicand input and a second multiplicand input and output a product, an adder configured to add the aligned addend and the product and output a sum without determining the sign of the sum or complementing the sum, a normalizer configured to receive the sum directly from the adder and normalize the sum irrespective of the sign of the sum and output a normalized sum, and a rounder configured to round and complement-adjust the normalized sum and output a final mantissa.

Apparatus and method for floating-point fused multiply add

Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths.

Computing half instructions of floating point numbers without early adjustment of the source operands

In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa to the adder. The operand adjust unit is coupled to receive a first operand and a second operand for a floating point add operation, and is configured to: right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands; to detect whether or not neither, one, or both of the first and second operands are subnormal numbers in parallel with at least a portion of the right shifting; and to left shift by one bit the right shifted mantissa responsive to only one of the first and second operands being a subnormal floating point number.

Subnormal number handling in floating point adder without detection of subnormal numbers before exponent subtraction

An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.

Apparatus and method for integer to floating-point format conversion

A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an exponent datapath of the floating point unit, where the 11-bit zero/one complement detect circuitry is used to determine a shift count for a right shifter in a large exponent difference mantissa datapath of the floating point unit. The 11-bit zero/one complement detect circuitry determines shift counts based on particular bit groupings of the 64-bit operand.

Method/apparatus for conversion of higher order bits of 64-bit integer to floating point using 53-bit adder hardware

A method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1) generating a shift count indicating the number of bit positions, if any, a mantissa of an unnormalized floating-point number is to be left shifted to normalize the unnormalized floating-point number, (2) generating a right shift indicator indicating the number of bit positions, if any, the mantissa is to be right shifted to normalize the unnormalized floating-point number, (3) incrementing the value of an exponent of the unnormalized floating-point number, (4) concurrently with the incrementing step, complementing a plurality of bits of the shift count and (5) adding the exponent, the shift count and the right shift indicator to generate an exponent of a normalized floating-point number. The method and circuit may be implemented in a floating-point adder.

Method and apparatus for high-speed exponent adjustment and exception generation for normalization of floating-point numbers

An arithmetic unit wherein a plurality of electrical signals corresponding to the mantissa is shifted and a bit signal corresponding to the sticky bit is calculated simultaneously with the calculation of the shift count. Initially, a serial approach to mantissa shifting and sticky bit calculation is employed. A parallel approach to matissa shifting and sticky bit calculation is adopted when all shift count bits are available. In one embodiment of the present invention, an exclusive OR gate is used to calculate the difference between the least significant bits of the first and second exponents. A shifter/sticky bit calculator immediately acts upon the output of the exclusive OR gate and begins shifting the mantissa and calculating the guard, round, and sticky bits. The more significant bits of the shift count are progressively generated thereafter, and the guard, round and sticky bits are calculated and the mantissa is shifted as the shift count bits become available. As soon as all shift count bits are available, a parallel approach to sticky bit calculation is adopted. Consequently, the shifted mantissa and the guard, round and sticky bits are available at the same time and much earlier than if the sticky bit were calculated according to known methods.

Growing community of inventors

Santa Clara, CA, United States of America

Sadar U Ahmed