National Semiconductor Corporation

Lsi Logic Corporation

Sadanand R Patil

Shaw Wei Lee

Nghia Thuc Tu

Nikhil Vishwanath Kelkar

Ashok S Prabhu

Alexander H Owens

Cheol Hyun Han

Jon M Long

Visvamohan Yegnashankaran

Mark R Schneider

Prabhansu Chakrabarti

Keith G Newman

Adrian S Murphy

Tai-Yu Chou

A method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having asymmetrical interconnect system for one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and 'L' shaped gold-bumped holes can be arranged on the same side of the ship in an opposing action, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chips surfaces, such that antenna substrates can be attached to both the top and bottom of the chip to form a product 'sandwich', whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.

Methods for manufacturing a radio frequency identification tag without aligning the chip and antenna

Techniques for forming micro-array style packages are disclosed. A matrix of isolated contact posts are placed on an adhesive carrier. Dice are then mounted (directly or indirectly) on the carrier and each die is electrically connected to a plurality of associated contacts. The dice and portions of the contacts are then encapsulated in a manner that leaves at least bottom portions of the contacts exposed to facilitate electrical connection to external devices. The encapsulant serves to hold the contacts in place after the carrier has been removed.

Universal lead frame for micro-array packages

A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

Electrical die contact structure and fabrication method

An apparatus and method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having a symmetrical interconnect system for attaching one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and 'L' shaped gold-bumped poles can be arranged on the same side of a chip in an opposing fashion, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chip surfaces, such that antenna substrates can attach to both the top and bottom of the chip to form a product 'sandwich,' whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.

Design of a two interconnect IC chip for a radio frequency identification tag and method for manufacturing same

A method and apparatus for the dicing of semiconductor wafers using pressure to mechanically separate the individual die from the wafer without the use of a wafer saw. The method includes forming trenches along the scribe lines on a semiconductor wafer and then applying a mechanical pressure to the semiconductor wafer. The mechanical pressure causes a 'clean break' of the wafer along the scribe lines, thereby singulating individual die on the wafer. The apparatus comprises a pad for supporting a semiconductor wafer and a positioning member to position the semiconductor wafer on the pad. A pressure mechanism is provided to apply a mechanical pressure to the wafer so as to singulate the individual die on the wafer.

Apparatus and method for dicing semiconductor wafers

A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages are disclosed. The described lead frames are generally arranged such that each device area has a plurality of contacts but no die attach pad. With this arrangement, the back surface of the die is exposed and coplanar with the exposed bottom surface of the contacts. A casing material (typically plastic) holds the contacts and die in place. In one aspect of the invention, the back surface of the die is metallized. The metallization forms a good attachment surface for the package and serves as a good thermal path to transfer heat away from the die. In another aspect, at least some of the contacts have a top surface, a shelf, and a bottom surface. The die is wire bonded (or otherwise electrically connected) to the shelf portions of the contacts. The described package is quite versatile. In some embodiments, the top surfaces of the contacts are also left exposed which provides a very low profile device that is particularly well suited for stacking. A stack of LLP devices can thus readily be provided or other devices can be stacked on top of the described devices. In some embodiments, a heat sink may be attached directly to the metallized bottom surface of the die or package. This tends to provide a good thermal path from the die. In another aspect of the invention, a lead frame panel suitable for use in packaging these semiconductor devices is described.

Leadless package

A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

Apparatus to decouple core circuits power supply from input-output

A metallic or ceramic dam structure surrounding a semiconductor die in a semiconductor device assembly is disclosed. The dam structure forms a cavity containing a potting compound encapsulating the die. The dam structure may also be provided with a flat lid portion, enclosing the cavity and forming a flat, exterior, heat-dissipating surface for the semiconductor device assembly. Further, an additional add-on structure, having heat dissipating fins, may be joined to the dam structure, exterior the semiconductor device assembly, to provide additional heat dissipation. The add-on structure is particularly well-suited to applications where air cooling is available.

Integral dam and heat sink for semiconductor device assembly

A first heat sink disposed immediately below and closely adjacent a semiconductor chip in a semiconductor chip assembly is disclosed. The heat sink is a flat metallic or ceramic shim. A second heat sink disposed immediately above and closely adjacent the semiconductor device is disclosed. The second heat sink preferably has a flat surface forming an exterior surface of the semiconductive device assembly . In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications where the semiconductor chip assembly is mounted to a thermal mass. The second heat sink is particularly well-suited to applications where air cooling is available. Each of the first and second heat sinks provide effective cooling, and when used together provide even more effective cooling.

Growing community of inventors

San Jose, CA, United States of America

Sadanand R Patil