Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Sadami Takeoka

Mitsuyasu Ohta

Osamu Ichikawa

Masayoshi Yoshimura

Akira Motohara

Takashi Ishimura

Seiji Kajihara

Takahiro Ichinomiya

Toshinori Hosokawa

Shinichi Yoshimura

Sudhakar Mannapuram Reddy

Toshihiro Hiraoka

A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for generating and outputting a predetermined number of pulses as the clock signal after a predetermined period has passed since a time when an output command signal was received. The clock control section has an oscillator circuit for generating and outputting the pulse, and is configured to output a last pulse of the predetermined number of pulses in a manner which holds a logical value immediately after an active edge for the scan path circuit.

Semiconductor integrated circuit, and designing method and testing method thereof

In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Semiconductor integrated circuit and method for testing the same

A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Method of designing semiconductor integrated circuit in which fault detection can be effected through scan-in and scan-out

A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device

In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so deserving to be detected cannot be reflected on the quality evaluation for the test sequences. To solve the problem, a 'design delay value' on a signal path, on which a corresponding delay fault is defined, is weighted. This invention thus provides 'methods of evaluating the quality of test sequences for delay faults' capable of evaluating the quality of the &#x201c;delay fault test sequences&#x201d; with more accuracy.

Methods for evaluating quality of test sequences for delay faults and related technology

Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.

Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same

A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

Semiconductor integrated circuit and testing method for the same

An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

All untestable delay faults are hardly calculated. Thus, when the fault coverage of an test sequence for a delay fault is calculated, the fault coverage is not calculated without excluding the number of untestable faults. Accordingly the fault coverage does not correctly represent a test quality. The delay faults are partly selected to analyze how many untestable delay faults exist among the selected delay faults. Thus, the, number of untestable delay faults included all the delay faults are estimated. Thus, a method for evaluating a delay fault test quality for calculating the fault coverage that correctly represents the test quality by using this value is provided.

Method for evaluating delay test quality

Method of designing semiconductor integrated circuit utilizing a scan test function

A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A test pattern is generated for the selected path so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a capture clock pulse is input to the circuit. Next, the test pattern generated is transformed into a normal scan pattern. Also, an expected output value, which should result from the test pattern input, is obtained. Then, the test pattern is input to the path under test and the resultant output value is compared to the expected value. In this manner, the path can be tested in such a manner as to see whether or not any hold error will occur.

Method for generating test pattern for semiconductor integrated circuit and method for testing semiconductor integrated circuit

Semiconductor device having a device for testing the semiconductor

A semiconductor integrated circuit ( ) includes first, second and second functional blocks ( and ). The first, second and second functional blocks ( and ) are coupled together via an inter-block signal line ( ). The first functional block ( ) includes: a logic circuit ( ); a test data output circuit ( ), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit ( ), which is connected between a selector ( ) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer ( ) that is made to have a high impedance by the testing standby circuit ( ); and a decision result output circuit ( ), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line ( ).

Functional block for integrated circuit, semiconductor integrated circuit, inspection method for semiconductor integrated circuit, and designing method therefor

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Osaka, Japan

Sadami Takeoka