Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Sachiyo Ito

Masahiko Hasunuma

Hisashi Kaneko

Akihiro Kajita

Takamasa Usui

Noriaki Matsunaga

Hiroshi Toyoda

Takashi Kawanoue

Hiroshi Tomita

Haruo Okano

Takashi Kawakubo

Nobuo Hayasaka

Junichi Wada

Keizo Shimamura

Junsei Tsutsumi

Masami Miyauchi

Hiroshi Yoshimura

Shohei Shima

Masamitsu Itoh

Naofumi Nakamura

Mie Matsuo

Hirokazu Ezawa

Kenji Shiraishi

Hiromitsu Mashita

Hideo Eto

Takeshi Nishioka

Makoto Saito

Taiga Uno

Tadayoshi Watanabe

Hirotaka Ichikawa

Tatsuhiro Oda

Masahiro Miyairi

Ken Furubayashi

Yuto Takeuchi

Masako Morita

Shinichirou Ooki

Rikyu Ikariyama

Kazuyuki Hino

A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.

Semiconductor memory device

According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system

According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.

Semiconductor device

According to one embodiment, a gas supply member is provided with a gas supply passage including a gas flow channel with a first diameter, and an exhaust port connected to one end portion of the gas flow channel and provided to a surface of a downstream side of the gas supply member. An yttria-containing film is formed on a surface constituting the exhaust port and the surface of the downstream side of the gas supply member. At least a part of the surface constituting the exhaust port is formed with a curved surface.

Gas supply member, plasma treatment method, and method of forming yttria-containing film

A solid-state image pickup apparatus includes an image pickup pixel unit in which a plurality of pixels each including a photoelectric conversion element and a field-effect transistor are arranged on a semiconductor substrate so that a light-receiving surface is disposed at a first surface side of the semiconductor substrate; a peripheral circuit unit provided at a periphery of the image pickup pixel unit of the semiconductor substrate; and a multilayered wiring layer in which a plurality of wiring layers for driving the field-effect transistor of the image pickup pixel unit are laminated at a second surface side of the semiconductor substrate, wherein a wiring in each of the wiring layers constituting the multilayered wiring layer is disposed so that a coverage of the wiring located at least in the image pickup pixel unit of the semiconductor substrate reaches 100%, viewed from the second surface side.

Back-illuminated type solid-state image pickup apparatus with peripheral circuit unit

A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

Stress analysis method, wiring structure design method, program, and semiconductor device production method

A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the low-relative-dielectric-constant-films, a plurality of plugs provided at least one within each of the interlayer-insulator-film and connected to a lower part of the wirings, and a plurality of reinforcement members provided at least one within each of the interlayer-insulator-film with being separated from the wirings at a predetermined interval, electrically cut from the wirings and the plugs, and at least partially located within the low-relative-dielectric-constant-films, and wherein, the interlayer-insulator-films, the wirings, the plugs, and the reinforcement members satisfy a predetermined relation for each of the interlayer-insulator-film.

A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.

A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.

A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.

Method of manufacturing semiconductor device

A semiconductor device is disclosed, which includes at least two layers superposed on each other in a stacking direction above a substrate, each of the layers including an insulating film a conductive layer films, a conductive plug electrically connected to the conductive layer, and at least one dummy via chain provided in the insulating films and stacked in the at least two layers, wherein the dummy via chain includes at least two reinforcing metal layers and at least one reinforcing plug.

There is disclosed a semiconductor device comprising a plurality of inter-level dielectric films which are stacked and provided in plural layers above a substrate, at least one first conductor which is provided in at least one inter-level dielectric film of the stacked inter-level dielectric films, and a plurality of second conductors which are provided in the inter-level dielectric film in which the first conductor is provided and which are connected to the lower surface of the first conductor and which are extended along the downward direction from the first conductor and further extended along a first direction and a second direction perpendicular to the first direction in such a manner as to be spaced apart from each other to form a lattice shape.

A semiconductor device includes an insulating film whose relative dielectric constant is 3.4 or less, at least one conductive layer, at least one conductive plug which is electrically connected to the conductive layer to form a conduction path, at least one reinforcing material whose Young's modulus is 30 GPa or more, at least one first reinforcing plug which is connected to the conductive layer and which is formed in contact with the reinforcing material, a reinforcing metal layer which is provided in the insulating film in an area other than that where the conductive layer is formed, and which is electrically disconnected from the conductive layer and the conductive plug, and a second reinforcing plug which is connected to the under side of the reinforcing metal layer and which is formed in contact with the reinforcing material.

A semiconductor device comprising a first insulating layer formed above a semiconductor substrate, and comprising a first insulating material, a second insulating material and a hole, a relative dielectric constant of the first insulating material being 3 or less, a Young's modulus of the first insulating material being 10 GPa or less, a linear expansivity of the first insulating material being greater than 30&#xd7;10&#xb0; C., and a linear expansivity of the second insulating material being 30&#xd7;10&#xb0; C.or less, and a second insulating layer formed on the first insulating layer, the second insulating layer having a groove connected to the hole, wherein a linear expansivity &#x3b1; of the first insulating layer within 6 &#x3bc;m from the hole is 30&#xd7;10&#xb0; C.or less, where vand &#x3b1;are a volume ratio and a linear expansivity of an i-th insulating material.

A photomask comprises a substrate, a translucent film selectively formed on the substrate, and a shading film selectively formed on the translucent film, wherein when the substrate, the translucent film and the shading film have Young's moduli (MPa) EEand E, and film thickness (m) d, dand drespectively, internal stresses (MPa) of the translucent film and the shading film at room temperature are sand srespectively, a covering rate by the translucent film defined by an area in which the shading film is not formed is expressed as h, and coefficients are expressed as k=1.3&#xd7;10, k=&#x2212;9.5&#xd7;10, k=6.0&#xd7;10, and k=&#x2212;5.2&#xd7;10respectively, the substrate, the translucent film and the shading film satisfy a condition given by the following expression: 

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Yokohama, Japan

Sachiyo Ito