Sharp Kabushiki Kaisha Corporation

Sachio Tsujino

Hajime Washio

Seijirou Gyouten

Yuhichiroh Murakami

Eiji Matsuda

Kazuhiro Maeda

Shunsuke Hayashi

Shuji Nishi

Keiji Takahashi

Yuichiro Murakami

Yasushi Kubota

Yasushi Sasaki

Satoshi Horiuchi

Yasuyoshi Kaise

Yousuke Nakagawa

Toshiya Aoki

Hoh Riku

Isao Ogasawara

Junichi Morinaga

Ichiro Shiraki

Etsuo Yamamoto

Keiichi Ina

Takehiko Kawamura

Yoshihiro Asai

Hiroyuki Ohkawa

Hiroaki Sugiyama

Nobuhiro Kuwabara

Shinya Takahashi

Ichiroh Shiraki

Mamoru Onda

Yuhji Asoh

A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.

Display driving device and display device having electric potential controlling circuitry

Provided is a technique of suppressing display defects such as flicker, without limiting the arrangement of data lines, in a liquid crystal display device having a display area in a non-rectangular shape. A liquid crystal display device includes an active matrix substrate 10, a counter substrate, and a liquid crystal layer. The active matrix substrate 10 includes a plurality of gate lines 11, and a plurality of data lines 12. In each of pixels defined by the gate lines 11 and the data lines 12, a pixel electrode 14 is arranged, and in a display area R, common electrodes 15 are provided. Outside the display area R, capacitance-generating parts C that generate capacitances between some gate lines 11 among the plurality of gate lines 11 and the common electrode are provided. The some gate lines 11 have lengths smaller than the gate lines having the maximum length, and intersect with some data lines 12 among the plurality of data lines 12. The capacitance-generating parts C are provided in such a manner that at least one capacitance-generating part C is provided with respect to one of the some gate lines 11.

Liquid crystal display device

By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C) and the gate of a MOS transistor (M), which outputs a signal in accordance with the potential of a storage node (N), are connected to the storage node (N). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N) upward to the threshold value of the MOS transistor (M) or higher is supplied to the second terminal of the storage capacitor in the readout period.

Photosensor operating in accordacne with specific voltages and display device including same

An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (), capacitors (C) and (C) have their respective first terminals connected with transistors (Q, Q) and (Q, Q) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (). The driver section () includes capacitors (C, C) connected with input terminals (Ti, Ti) for respective supply of clock signals DCK, DCKB each having a voltage alternating between &#x2212;VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK, DCKB which are supplied to second terminals of the capacitors (C, C) respectively. In this arrangement, the driver sectiongenerates signals each having a voltage alternating between VDD and 3VDD, as the control signals.

Power supply circuit and display device including the same

An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.

The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal. In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

Monolithic driver-type display device

A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Level shifter circuit and display device provided therewith

An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

Display device having display area and non-display area, and driving method thereof

A liquid crystal display apparatus () wherein the shift registers of a source driver () are configured by use of asynchronous RS flip-flops in which an active input to a set input terminal has a higher priority than an active input to a reset terminal. In a second mode of operation, first and second clock signals and a start pulse are fixed at high levels, thereby performing discharges from all the pixels (PIX) of a liquid crystal panel ().

Display apparatus and method for driving the same

A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn&#x2212;1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn&#x2212;1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Shift register and display device using same

A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SLthrough SLn not to overlap each other.

Shift register and display device using the same

The data signal line driving circuit of the present invention is arranged so that data signal line groups, each of which is made up of two data signal lines sequentially disposed, are connected to two video signal lines, each of which allows a two-phased video signal to be forwarded. A shift register SR, a drive switching circuit, and a waveform shaping circuit, that constitute a video signal fetching section, collect the data signal line groups via the two video signal lines as a single block. At this time, the data signal lines are respectively driven so as to fetch the video signal from the video signal lines into the data signal lines of the data signal line groups in each block. Thus, in performing multiphase development, it is possible to provide the data signal line driving circuit which can reduce power consumption in low resolution driving compared with a case of high resolution driving.

Data signal line driving method, data signal line driving circuit, and display device using the same

A simultaneous precharge type display device source driver includes supply control circuits each of which is provided on each of source bus lines. Each of the supply control circuits receives (a) a precharge control signal for precharging each of the source bus line and (b) a sampling control signal for writing data, which should be written on pixels, onto the source bus line. The one of two switches turns ON in response to the precharge control signal and the sampling control signal. The other of the switches turns ON in response to the sampling control signal. In the sampling operation, both the switches are turned ON so as to quicken the writing operation. In the precharge operation, the other switch does not operate, so that it is possible to reduce the power consumption.

Display device driving circuit, display device, and driving method of the display device

In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A, A, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X, X, . . . ) obtained by extracting a period when the output signal A (A, A, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q, Q, . . . ) from a corresponding flip-flop is High. The output signal X (X, X, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.

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Yao, Japan

Sachio Tsujino