Kabushiki Kaisha Toshiba

Nippon Zeon Company, Ltd.

Toshiba Electronic Devices & Storage Corporation

Sachio Hayashi

Yoichiro Kubo

Yoshiaki Aimura

Noboru Watanabe

Motofumi Oyama

Reiko Nojima

Isamu Miyauchi

Tyusei Ogawa

According to one embodiment, a circuit design support apparatus includes: a first specifying unit that specifies a first element generating negative potential; a second specifying unit that specifies a criterion of a current flowing to a substrate from an electrode of a second element arranged in a peripheral area of the first element due to a parasitic element; a calculation unit that calculates a criterion violation rate under a condition where a location of the second element has been shifted to one of a plurality of places; and a display processing unit that displays, on a display, information indicating the criterion violation rate such that the information is superimposed on a layout.

Circuit design support apparatus and circuit design support method

A semiconductor device includes a semiconductor chip including first to fourth pads, and first and second switches. The first switch includes first and second nodes coupled to the first and second pads and sends from the second node a current larger than a threshold flowing in from the first node. The second switch includes third and fourth nodes coupled to the third and fourth pads and sends from the fourth node a current larger than a threshold flowing in from the third node. The third and fourth nodes are not coupled to any nodes of high and low potentials of any circuit which receives the potentials to operate. A first wire is coupled to the first pad and the first conductor, and a second wire is coupled to the second pad and the second conductor.

Semiconductor device, semiconductor chip, and method of manufacturing semiconductor device

According to one embodiment, a chip model generating unit and a counter tester ground capacitance adding unit are provided. The chip model generating unit generates a chip model based on an ESD protection circuit network model to which an inter power net capacitance of a semiconductor chip is added. The counter tester ground capacitance adding unit adds a counter tester ground capacitance to the chip model.

ESD analysis apparatus

A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, includes extracting an electrostatic discharge protection network including pads, nets and protective elements; setting start pads and end pads in the electrostatic discharge protection network; finding inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths from the start pads to the end pads; grouping together the electrostatic discharge current paths in the same order; calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads and groups to which the start pads and the end pads belong using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages; and determining whether the layout passes testing regarding electrostatic discharge.

Electrostatic discharge testing method and semiconductor device fabrication method

A semiconductor integrated circuit electrostatic discharge analysis apparatus includes a resistance network generation unit generating a resistance network served as a power supply interconnect equivalent circuit in a logic cell region of a semiconductor LSI circuit based on pitch, width and a sheet resistance of a power supply interconnect; a protection network generation unit generating an electrostatic discharge protection network with pads and protection elements placed in an I/O cell region of the changing semiconductor LSI circuit, connected to the resistance network; and an analysis unit calculating an inter-pad voltage between the pads when electrostatic discharge equivalent current flows between the pads.

Analysis apparatus for semiconductor LSI circuit electrostatic discharge by calculating inter-pad voltage between pads

An electrostatic discharge analysis method includes extracting the pads from an input layout of the semiconductor integrated circuit; extracting the nets connected to the extracted pads; extracting the protective elements connected to the extracted nets; forming connection nodes that connect the pads or the protective elements to the nets; extracting for each net, distributed resistances that distribute along the net; connecting the distributed resistances to the connection nodes in place of the nets; forming inter-resistance nodes between the distributed resistances; and calculating an inter-pad voltage when flowing electrostatic discharge current between the pads.

Method of analyzing semiconductor LSI circuit electrostatic discharge

A technique for effectively attenuating EMI noise, which is generated from the electric power system of semiconductor devices, is described. In accordance with the technique, a power supply netlist with an additional electric current source(s) is generated by adding block power supply current waveform data, as extracted from test vector data and a block netlist, to the power supply netlist as extracted from the layout data of the circuit under analysis. A circuit simulation of the power supply netlist with an additional electric current source(s) is then performed in order to calculate power supply current/voltage waveform data. Furthermore, current/voltage spectral data is calculated by the Fourier transformation of the power supply current/voltage waveform data followed by displaying the current/voltage spectral data as the result of the Fourier transformation.

Device and method for analyzing EMI noise and semiconductor device

A layout pattern generation method and device executing this method in which a symbolic layout of a semiconductor integrated circuit is generated, the sizes of transistors are changed by using the circuit connection information of the layout pattern, the correspondence information of the transistors whose sizes have been changed are generated by using the symbolic layout and the changed circuit connection information, the symbolic layout after the transistor sizes have been changed is generated by using the correspondence information, the generated symbolic layout is compacted, and then a new layout pattern is generated by using the compacted layout pattern.

Layout pattern generation device for semiconductor integrated circuits

A method for performing compaction of a layout of a semiconductor integrated circuit designed in a hierarchy is described. The compaction of the layout is carried out by repeating a single level compaction process for compacting cell layouts in one of the hierarchical levels from a lowest level to a highest level of the hierarchical levels. The single level compaction process comprises a first replacement step of replacing lower level cell layouts in a current level cell layout with abstract cell layouts having the same profile and the same positions of terminals to be connected to the current level cell layout as the lower level cell layouts have in advance of compaction. The compaction of the current level cell is performed under a constraint that the relocations of the terminals of the current level cell layout after compaction from the original positions before compaction are possible within prescribed ranges. After compaction, the abstract cell layouts is replaced by the lower level cell layouts.

Method of compacting layouts of semiconductor integrated circuit

A vulcanizable rubber composition including a partially hydrogenated unsaturated nitrile-conjugated diene copolymer having an iodine value of smaller than 25, a sulfur vulcanizer and a tellurium dithiocarbamate compound as a vulcanization promotor. This rubber composition provides a vulcanizate having reduced heat build-up, reduced compression set and high mechanical strength.

Vulcanizable partially hydrogenated nitrile rubber composition

A nitrile group-containing, highly saturated copolymer rubber is disclosed, the copolymer chain of which is comprised of (1) 5 to 40% by weight of units of an unsaturated nitrile monomer, (2) 1 to 80% by weight of units of a monomer selected from a fluorine-free unsaturated carboxylic acid ester monomer and a fluorine-containing vinyl monomer and (3) up to 20% by weight of units of a conjugated diene monomer, with the balance being (4) units of a hydrogenated conjugated diene monomer, wherein the sum of the contents of the monomer units (1) and (2) is 30 to 90% and the sum of the contents of the monomer units (3) and (4) is 10 to 70% by weight. This copolymer rubber results in a rubber composition having an improved cold resistance.

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Tokyo, Japan

Sachio Hayashi