Samsung Electronics Co., Ltd.

Sachin Suresh Upadhya

Kyungsoo Kim

Jinin So

Jonggeon Lee

Eldho Pathiyakkara Thombra Mathew

Rengaraja Sudarmani

Uday Kumar N B

Mayuresh Jyotindra Salelkar

Prathiksha Gautham

Abhinav Sharma

A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

Methods of operating a near memory processing-dual in-line memory module (NMP-DIMM) for performing a read operation and an adaptive latency module and a system thereof

The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.

Method and system for validating a memory device

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Bengaluru, India

Sachin Suresh Upadhya