Arm Limited

Nvidia Corporation

Sachin Satish Idgunji

David Walter Flynn

Jonah Matthew Alben

Jue Wu

Robert Campbell Aitken

Emmett Michael Kilgariff

Bal S Sandhu

Dale L Kirkland

Vikas Chandra

Rouslan Lyubomirov Dimitrov

Shantanu Sarangi

Hemangi Umakant Gajjewar

Siddharth Sharma

Gus Wai-Yan Yeung

Tezaswi Raja

Emre Özer

Thomas Edward Dewey

Narayan Kulshrestha

James P Reilley

Ramachandiran V

Yew Keong Chong

Shidhartha Das

David Michael Bull

James Edward Myers

Ming Yiu Siu

Rajeshwaran Selvanesan

Manan Patel

Gregory Munson Yeric

Lordson L Yue

David William Howard

Hsin-Yu Chen

Donald Kenneth Felton

Arvind Gopalakrishnan

Amit Pabalkar

Wen Yueh

Siddharth Saxena

Chad Plummer

Aniket Naik

Ewa Kubalska

Kartik Joshi

Vincent Phillipe Schuppe

Anand Shanmugam Sundararajan

Ben Faulkner

Vinayak Bhargav Srinath

Ben Pei En Tsai

Jun (Alex) Gu

Siddharth Bhargav

Imran Iqbal

Bardia Zandian

Leah Elizabeth Schuth

Justin Tai

Alex Gu

Lordson Yue

Abhijeet Chandratre

Archana Srinivasaiah

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

Leveraging low power states for fault testing of processing cores at runtime

Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.

Real-time hardware-assisted GPU tuning using machine learning

An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

Core off sleep mode with low exit latency

Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

Fault injection architecture for resilient GPU computing

In various examples, one or more components or regions of a processing unit&#x2014;such as a processing core, and/or component thereof&#x2014;may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

An integrated circuit such as, for example a graphics processing unit (GPU), includes a dynamic power controller for adjusting operating voltage and/or frequency. The controller may receive current power used by the integrated circuit and a predicted power determined based on instructions pending in a plurality of processors. The controller determines adjustments that need to be made to the operating voltage and/or frequency to minimize the difference between the current power and the predicted power. An in-system reinforced learning mechanism is included to self-tune parameters of the controller.

Techniques for efficiently operating a processing system based on energy characteristics of instructions and machine learning

Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

Optimal operating point estimator for hardware operating under a shared power/thermal constraint

A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.

Clock gating coupled memory retention circuit

Introduced herein is an improved technique of recovering system frequency margin via distributed CPMs. The introduced technique creates and distributes multiple sets of always sensitized critical path replicas across a chip and monitors them for timing failure. The introduced technique takes feedback from these critical path replicas and dynamically boosts the clock frequency of the chip to remove the margin. The introduced technique provides more accurate and more comprehensive coverage of a chip performance.

System frequency margin recovery via distributed critical path monitors (CPM)

An integrated circuit such as, for example a graphics processing unit (GPU), having an on-chip analog to digital converter (ADC) for use in overcurrent protection of the chip is described, where the overcurrent protection response times are substantially faster than techniques with external ADC. A system-on-chip (SoC) includes the integrated circuit and a multiplexer arranged externally to the chip having the ADC, where the multiplexer provides the ADC with a data stream of sampling information from a plurality of power sources. Methods for overcurrent protection using an on-chip ADC are also described.

Voltage/frequency scaling for overcurrent protection with on-chip ADC

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San Jose, CA, United States of America

Sachin Satish Idgunji