Mie Fujitsu Semiconductor Limited

Suvolta, Inc.

Sachin R Sonkusale

Lucian Shifren

Pushkar Ranade

Scott E Thompson

Weimin Zhang

Paul E Gregory

Thomas Hoffmann

Sameer S Pradhan

Teymur Bakhishev

Lance A Scudder

Dalong Zhao

Sung Hwan Kim

Jing Wang

Michael Duane

Lingquan Wang

Yujie Liu

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5&#xd7;10dopant atoms per cm. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Advanced transistors with punch through suppression

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.

Method for fabricating a transistor device with a tuned dopant profile

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;Vcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Low power semiconductor transistor structure and method of fabrication thereof

A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.

Semiconductor structure and method of fabrication thereof with mixed metal types

A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.

Deeply depleted MOS transistors having a screening layer and methods thereof

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1&#xd7;10atoms/cm, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Source/drain extension control for advanced transistors

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1&#xd7;10atoms/cm', or alternatively, less than one-quarter the dopant concentration of the source and the drain.

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Sachin R Sonkusale