Freescale Semiconductor,inc.

Nxp B.v.

Freecsale Semiconductor, Inc.

Sachin Prakash

Arvind Kaushik

Inayat Ali

Rahul Garg

Somvir Dahiya

Rajan Kapoor

Raghavendra Srinivas

Arindam Sinha

Nitin Kumar Jaiswal

Nandan Tripathi

Apoorv Goel

Vivek Goel

Anshul Jain

A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

System and method for managing access to registers

For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

Hardware-based time alignment of wireless links

A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Timing synchronization circuit for wireless communication apparatus

An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

System for recovering unresponsive common public radio interface (CPRI) nodes

A method and system for managing communications between sub-systems of a communication device. The sub-systems include a Radio Frequency Integrated Circuit (RFIC) and a Baseband Integrated Circuit (BBIC). The BBIC includes a processing engine, a state machine module and an interface module. The method includes initializing a Digital Radio Frequency Third Generation (DigRF3G) interface between the RFIC and the BBIC. The processing engine is kept functionally inactive during the initialization process of the DigRF3G interface. Further, the method includes exchanging one or more packets between the RFIC and the BBIC.

Method and system for initializing an interface between two circuits of a communication device while a processor of the first circuit is inactive and waking up the processor thereafter

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Noida, India

Sachin Prakash