Cirrus Logic Inc.

Cirrus Logic International Semiconductor Limited

Sachin Deo

Nariankadu Datatreya Hemkumar

Younes Djadi

Eric B Smith

Nathan Daniel Pozniak Buchanan

Daniel T Bogard

Raghunath Krishna Rao

Junsong Li

Miroslav V Dokic

Wai-Shun Shum

Vladimir Mesarovic

James P McFarland

Akhilesh Persha

Nathan Buchanan

Nariankadu Datareya Hemkumar

Roshan Kamath

Franz Weller

Nariankadu D Hemkumar

A system includes primary and secondary devices (e.g., camera controllers that drive voice coil motors) each having respective outputs and a communication link. The primary device includes first and second hardware timers, each of which expires at a time derived from a periodic control loop trigger. At first timer expiration, the primary transmits first updated values to the secondary. At second timer expiration, primary device hardware picks up and applies second updated values to the primary device outputs. In response to receiving the first updated values from the primary device, the secondary device applies the received first updated values to its outputs. The primary/secondary device combination provide a sufficient number of total outputs that they could not individually provide and further synchronize the outputs with small skew through the timers, which are programmable to also accommodate processing of inputs (e.g., from voice coil motor sensors) to compute the outputs.

System and method for providing increased number of time synchronized outputs by using communicating primary and secondary devices

A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and based on position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The primary and secondary camera controller devices receive respective primary and secondary sensor data from the position sensors, send the respective primary and secondary sensor data to the other camera controller device via the communication link, process the primary and secondary sensor data and the position information to generate respective primary and secondary control data, and drive the respective primary and secondary control data to the actuators concurrently.

Multi-chip camera controller system with inter-chip communication

A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the secondary camera controller device. The primary camera controller device processes the received sensor data and the received position information to generate control data, sends a secondary portion of the control data to the secondary camera controller device via the communication link, and drives a primary portion of the control data to the actuators. The secondary camera controller device drives the received secondary portion of the control data to the actuators concurrently with the primary camera controller device driving the primary portion of the control data to the actuators.

A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

Systems and methods for context-dependent multicore interrupt facilitation

A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

Flexible latency-minimized delivery and management of disparate-rate data streams and sub-streams for processing

A system for atomically transferring vectors of data from a transmitter of the vectors of data to a receiver of the vectors of data may include a plurality of memory buffers configured to store the vectors of the data, each buffer configured to store one vector of the vectors of data at a time, the plurality of memory buffers comprising at least three memory buffers and a controller for controlling the plurality of memory buffers. The controller may be configured to, responsive to a condition for transferring information represented by the vectors of data to the receiver, determine which of the plurality of buffers from which the receiver may receive most-recently updated information completely written to the plurality of buffers by the transmitter. The controller may further be configured to, responsive to a condition for updating information represented by the vectors of data, determine which of the plurality of buffers for the transmitter to write updated information without blocking atomic receipt by the receiver of information from a most-recently updated buffer.

Flexible, non-blocking asynchronous transfer of time-variant atomic data

A system for reading a plurality of subset views of an evolving data store may include for each subset view, a plurality of memory buffers comprising at least three buffers. The system may also include control circuitry for controlling the plurality of memory buffers of the plurality of subset views, the control circuitry configured to maintain, for each subset view, a variable defining a most-recently updated buffer of the plurality of buffers such that a read request for such subset view will respond with data of the most-recently updated buffer of such subset view; and responsive to an update of data of the evolving data store: (i) determine, for each subset view, a selected data buffer of the plurality of buffers other than the most-recently updated buffer for such subset view to write updated subset view information; (ii) cause, for each subset view, the updated subset view information for such subset view to be written to the selected data buffer for such subset view; and (iii) substantially simultaneously across all of the plurality of subset views, update the variables defining the most-recently updated buffer of the plurality of subset views such that a subsequent read request for a subset view will respond with the updated subset view information for such subset view.

Discrete exchange and update of multiple consistent subset views of an evolving data store

A method of decoding an encoded bitstream. The method includes performing a two-table lookup. A first table is addressed in response to a first plurality of bits from the bitstream. An address into a second table is generated using a value in an entry in said first table accessed in the addressing step. A value (representing the decoded value corresponding to the codeword in the bitstream) in an entry in said second table at the address from the generating step is output.

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Austin, TX, United States of America

Sachin Deo