Qualcomm Incorporated

Sachin Bapat

Mohamed Hassan Abu-Rahma

Martin Saint-Laurent

Animesh Datta

Ramaprasath Vilangudipitchai

Seid Hadi Rasouli

Prayag Bhanubhai Patel

Jay Madhukar Shah

Saravanan Marimuthu

Peeyush Kumar Parkar

Sakthivel Packirisamy

A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Flip-flop with reduced retention voltage

An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.

Method and apparatus for clock power saving in multiport latch arrays

Growing community of inventors

Bengaluru, India

Sachin Bapat