Kabushiki Kaisha Toshiba

Sachiko Kobayashi

Toshiya Kotani

Satoshi Tanaka

Kazuko Yamamoto

Koji Hashimoto

Soichi Inoue

Taiga Uno

Suigen Kyoh

Susumu Watanabe

Hisashi Kaneko

Takamasa Usui

Masahiko Hasunuma

Masami Aoki

Hiromitsu Mashita

Fumiharu Nakajima

Kiyomi Koyama

Shimon Maeda

Atsuhiko Ikeuchi

Hirotaka Ichikawa

Hisako Aoyama

Mitsuhiro Yano

Masanari Kajiwara

Shinichiroh Ohki

Hirotaka Ichiakwa

A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Pattern correcting method, mask forming method, and method of manufacturing semiconductor device

A pattern forming method including modifying design data subjected to a first design rule check in design data of a pattern to be formed in a semiconductor substrate, performing the first design rule check to the modified design data again, outputting the modified design data which does not violate the first design rule as pattern forming design data used in actual pattern formation, and performing a second design rule check having an allowable range wider than that of the first design rule to the modified design data which violates the first design rule, and outputting the modified design data which does not violate the second design rule as the pattern forming design data, and redesigning the pattern to satisfy the second design rule or adjusting the modification guideline such that the modified design data which violates the second design rule satisfies the second design rule.

Pattern forming method and pattern verifying method

A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include the first modification area by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area.

Layout generating method for semiconductor integrated circuits

Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

Mask data processing method for optimizing hierarchical structure

A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

Method and program for pattern data generation using a modification guide

A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing system comprising a storage device storing processing data for semiconductor integrated circuits processed in the past, a plurality of operation processing modules, a module selecting section selecting at least one operation processing modules, an optical proximity effect correction section executing optical proximity effect correction to a processing object data and generating a correction data by utilizing past correction information applied for a stored data equivalent to the processing object data, a converting section converting the processing object data into mask data, and a drawing system drawing a mask pattern based on the mask data.

Mask manufacturing system, mask data creating method and manufacturing method of semiconductor device

A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting a marginless point in the processed mini-data where a process margin is less than a predetermined threshold in a manufacturing process of the semiconductor device, determining a class of the marginless point in accordance with a criticality and a category of the marginless point, determining a parameter and a range of the parameter used for the marginless point in accordance with the class of the marginless point, and generating a plurality of test patterns to which different values of the parameter are respectively applied within the range.

Method for generating test patterns utilized in manufacturing semiconductor device

A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Pattern correction method of semiconductor device

A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.

Mask pattern generating method and manufacturing method of semiconductor apparatus

A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.

Mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus

A pattern of exposure mask-use design data having a hierarchical structure is corrected in order to finish with fidelity a transfer pattern to be formed on a wafer, in which if the exposure apparatus has a light source shape that does not have rotation symmetry at any given angle around an optical axis, as the center, of an illumination optics or a projection optics, a cell A rotated in arrangement in input data having a hierarchical structure is replaced with a cell A&prime; not employing rotation and then optical proximity correction is effected.

Pattern correcting method and pattern verifying method

A correction target segment extracted from the design pattern is divided into lengths suited for correction. If the arrangement of the divided segments is a one-dimensional pattern, a correction value is obtained by conducting a one-dimensional process simulation to an arrangement within a predetermined distance from a divided segment in perpendicular direction. If the arrangement of the divided segments is a two-dimensional pattern, a correction value is obtained by two-dimensionally extracting a pattern included in a rectangular region having a predetermined distance from one point on the divided segment in perpendicular and horizontal directions and by conducting a two-dimensional process simulation to the extracted pattern.

Mask data design method

A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.

Method of manufacturing semiconductor device

This invention is provided to eliminate the optical proximity effect which will occur because of different rates of dimensional change between before and after etching when a plurality of gate materials are etched in a single device. After a to-be-corrected region is extracted, an n.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the n.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be a p.sup.+ -type polysilicon gate layer, thereby correcting the size of the n.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the n.sup.+ -type polysilicon gate layer. After that, a p.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the p.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be an n.sup.+ -type polysilicon gate layer, thereby correcting the size of the p.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the p.sup.+ -type polysilicon gate layer.

Mask pattern correction method

In a Levenson photomask design method of partially forming a plurality of opening patterns for passing incident light in a light-shielding film for shielding the incident light, and arranging, on some patterns, phase shifters, line segment pairs of different patterns which are adjacent to each other within a predetermined distance R are extracted in units of line segments obtained by dividing the patterns. A pattern within a predetermined distance S from the central point of the opposite region of a line segment pair of interest in a direction perpendicular to the line segments is obtained. The obtained pattern is subjected to a process simulation to obtain resolution easiness representing the easiness in resolving the adjacent patterns. On the basis of the resolution easiness obtained for the adjacent pattern pair within the distance R, a phase shifter is arranged in ascending order of resolution easiness to give a phase difference. Resolution suitable for the exposure condition used can be obtained by a simple method. When the shifter arrangement is determined in consideration of the resolution easiness, a high-resolution shifter arrangement can be realized for a Levenson phase shift mask.

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Ichikawa, Japan

Sachiko Kobayashi