Toyota Jidosha Kabushiki Kaisha

Kabushiki Kaisha Toyota Chuo Kenkyusho

Sachiko Kawaji

Tsutomu Uesugi

Takashi Suzuki

Takahide Sugiyama

Koji Hotta

Masanori Usui

Masayasu Ishiko

Toshio Murata

Hiroaki Tanaka

Jun Saito

Tomoyoshi Kushida

Katsuhiko Nishiwaki

Masahito Kodama

The semiconductor device has a collector electrode, a pcollector region formed on the collector electrode, an ndrift region formed on the collector region, a pbody region formed on the drift region, and a plurality of nemitter regions formed within the body region. The emitter regions are connected to an emitter electrode. A plurality of trench gate electrodes is formed within the body region. Each trench gate electrode opposes, via an insulating layer, a portion of the body region separating the drift region and the emitter region. The body region is divided into a plurality of body sections, and the body sections are classified into two groups. One group has the emitter region within the body section, and the other group has no emitter region within the body section. A plurality of first trenches is formed within the body section having no emitter region. A pcontact region is formed between the first trench and the trench gate electrode.

Semiconductor devices

The present invention relates to a technique for reducing the on-voltage of the semiconductor device by increasing the concentration of minority carriers in the deep region () and the intermediate region (). A semiconductor device according to the invention comprises an electrode, a top region () of a second conductivity type connected to the electrode, a deep region of the second conductivity type, and an intermediate region of a first conductivity type connected to the electrode. A portion of the intermediate region isolates the top region and the deep region. The semiconductor device further comprises a gate electrode () facing the portion of the intermediate region via an insulating layer. The portion facing the gate electrode isolates the top region and the deep region. The semiconductor device according to the invention further comprises a barrier region () that is formed within the intermediate region and/or the top region.

Trench gate field effect devices

The present invention provides a technique for accumulating minority carriers in the body region, that is, the intermediate region interposed between the top region and the deep region, and thus increasing the concentration of minority carriers in the intermediate region. A semiconductor device has a top region () of a second conductivity type, a deep region () of the second conductivity type, and an intermediate region () of a first conductivity type for isolating the top region and the deep region. The semiconductor device further has a trench gate () facing a portion of the intermediate region via an insulating layer (). The portion facing the trench gate isolates the top region and the deep region. The trench gate extends along a longitudinal direction. The width of the trench gate is not uniform along the longitudinal direction; instead the width of the trench gate varies along the longitudinal direction.

The dense accumulation of hole carriers can be obtained over a wide range of a semiconductor region in a floating state formed within a body region of an IGBT. An n type semiconductor region () whose potential is floating is formed within a ptype body region (). The n type semiconductor region () is isolated from an ntype emitter region () and an ntype drift region () by the body region (). Furthermore, a second electrode () is formed, so as to oppose to at least a part of the semiconductor region () via an insulator film (). The second electrode () does not oppose to the emitter region ().

It is intended to provide a high withstand voltage field effect type semiconductor device that relaxes electric fields in a semiconductor substrate without thickening thickness of a drift region and achieves withstand-ability against high voltage without sacrificing ON-voltage, switch-OFF characteristics, and miniaturization. A field effective type semiconductor device comprises emitter regionsand gate electrodesand the like on a surface (upper surface in FIG.), a collector regionand the like on the other surface (lower surface in FIG.), wherein Nfield dispersion regionsof low impurity concentration are arranged between P body regionsfacing to gate electrodesand an N drift regionbelow P body regions. Thereby, electric field between collector and emitter is relaxed and high withstand voltage field effect type semiconductor device is realized. Another field dispersion region can be arranged between the N drift regionand Pcollector regionbelow the N drift region

High withstand voltage field effect semiconductor device with a field dispersion region

A semiconductor device containing a lateral MOS transistor comprising a silicon substrate, an n-type first semiconductor layer constituting a drain drift region, a p-type second semiconductor layer prepared within the first semiconductor layer to constitute a body region and with a channel region formed within a portion of said body region, an n-type third semiconductor layer prepared on the surface of the second semiconductor layer to constitute a source region, an n-type fourth semiconductor layer constituting a drain region, and an insulation layer that is constituted of insulating material filled into a trench prepared in the first semiconductor layer and arranged along the two sides of the drain region. The drain region is formed into a region deeper than the insulation layer and in contact with the drain drift region at a portion beneath the insulation layer. The semiconductor device provides a high breakdown voltage and a low on-resistance, and can be fabricated with a reduced cell pitch.

Semiconductor device containing a lateral MOS transistor

The MOS gate thyristor of the present invention has a p,type anode layer (first semiconductor layer), an n,type base region (second semiconductor layer) with the function of acting as a drift layer, a p,type base region (third semiconductor layer), and an n,type impurity diffusion layer (fourth semiconductor layer) with the function of acting as a source region. On the surface of the base region, an n,type floating emitter region (fifth semiconductor layer) is formed, while a first channel region (sixth semiconductor layer) is formed between the impurity diffusion layer and the floating emitter region. At the lower ends of the fourth semiconductor layer and the first channel region an insulation layer is formed. The insulation layer acts to suppress the operation of a parasitic thyristor to ensure a reliable turn-off operation of the transistor. A portion of the semiconductor extends from the n,type floating emitter region and lies underneath the insulation layer in the direction alongside the principal plane of the p,type anode layer. The extended semiconductor portion helps broaden the carrier injection path.

Semiconductor device

Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate. The semiconductor device of the present invention prevents a high electric field at a corner of the bottom of the trench gate, thus achieving its high breakdown voltage.

Semiconductor device including lateral MOS element

A MOSFET wherein the formation of a channel in a channel formation region is controlled by a voltage applied to an insulated gate, comprising: a semiconductor substrate; a first semiconductor layer (drain region) of a first conductivity type formed on a surface of the semiconductor substrate; a second semiconductor layer (body region) of a second conductivity type provided within the first semiconductor layer, where a part thereof forms the channel formation region; a third semiconductor layer (source region) of the first conductivity type provided selectively in the second semiconductor layer; and a body contact region in electrical contact with the second semiconductor layer. The body contact region is formed in an area that is separated from an active region by a non-active region. With this structure, parasitic bipolar transistors operate simultaneously throughout the entire device so that a uniform breakdown current is generated, thus preventing element destruction due to current concentrations.

Growing community of inventors

Owariasahi, Japan

Sachiko Kawaji