Mitsubishi Denki Kabushiki Kaisha

Sachie Kuroda

Takashi Yamasaki

The microcomputer comprises: a CPU, a DRAM installed within the microcomputer, a non-volatile memory storing a program data therein, an interface commonly used among various circuits within the microcomputer, a system clock generating circuit, which generates clock signals, and is also capable of suspending and regenerating the clock signals, respectively in response to a system clock stop signal and a system clock generation signal, a peripheral circuit which is capable of outputting an interrupt signal requesting the system clock generation to the CPU, and a control circuit which re-transmits the program data from the non-volatile memory to the DRAM in response to a re-initialize request signal output from the CPU, and also outputs an access prohibition, signal for prohibiting the access to the data stored in the DRAM and an access prohibition release signal for releasing the prohibition of access. Due to this construction, it no longer requires two clock generating circuits; namely a clock generating circuit one for the system and that exclusively used for the DRAM, and thus the function and the level of integration of the microcomputer are not degraded.

Microcomputer with re-initialization of DRAM or SRAM using non-volatile memory

A DMA control system continuously grants permission to access the I/O device and memory to continue data transfer in a cycle steal mode when there is a continuous stream of DMA requests from a number of I/O devices by producing a logical sum of the DMA requests.

DMA control for continuing transfer to input/output device in a cycle

A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.

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Itami, Japan

Sachie Kuroda