Intel Corporation

Sachidanandan Sambandan

Duane R Mills

Richard D Pashley

Brian L Dipert

Bruce McCormick

Phillip M Kwong

Kevin W Frary

Kerry Dean Tedrow

Jahanshir J Javanifard

Sanjay S Talreja

Robert J Johnston

Peter K Hazen

Sherif R Sweha

Tuong P Trieu

David A Leak

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

Synchronous interface for a nonvolatile memory

A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

Asynchronous interface for a nonvolatile memory

A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.

Flash memory including a mode register for indicating synchronous or

An output buffer circuit including different arrangements of output devices selectable by circuitry which tests the load characteristics to provide different buffer drive strengths, and different paths having different current carrying characteristics for enabling the output devices selectable by the circuitry which tests the load characteristics to vary the slew rate of the output devices to best match the load.

Output buffer with current paths having different current carrying

An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.

Method and apparatus for performing burst read operations in an

A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.

Pipelined read architecture for memory

Noise on address lines is prevented from causing incomplete preparation for reading data after an address transition is detected. One ensures that a flash memory device reads correct data by guaranteeing that each address transition detection, including false address transition detections caused by noise, permits sufficient preparation to read data reliably. An address detected pulse is generated whenever at least one bit of an address changes. If noise causes an invalid address transition detected pulse that is too short to occur, the short pulse will be extended to permit preparation for the memory to be read. Input summation circuitry receives an input pulse and combines the input pulse with a feedback signal to form an input sum signal. Feedback circuitry receives the input sum signal and outputs the feedback signal to the input summation circuitry. The feedback signal holds the input sum signal until the feedback circuit is reset. Delay circuitry receives the input sum signal and, after a predetermined delay, provides as output a delayed signal that prepares the delay circuitry to reset and that also causes the feedback circuitry to reset (i.e., no longer output the feedback signal). Cessation of the input sum signal causes the delay circuitry to reset and halt output of the delay signal. Output summation circuitry receives the input sum signal and combines the input sum signal with the delay signal to form an output sum signal.

Method and circuitry for generating a safe address transition pulse in a

A nonvolatile memory device is described. The memory device includes a main memory array for storing data. The main memory array comprises a first block and a second block. A redundant memory array comprises a first redundant block and a second redundant block. The first redundant block comprises a first redundant column of memory cells and a second redundant column of memory cells. The second redundant block comprises a third redundant column of memory cells and a fourth redundant column of memory cells. A content addressable memory (CAM) comprises a first set of CAM cells for storing a first address of a first defective column in the main memory array and a second set of CAM cells for storing a second address of a second defective column in the main memory array. The first set of CAM cells cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block. The first set of CAM cells cause the third redundant column in the second redundant block to replace the first defective column when the first defective column is in the second block. The second set of CAM cells cause the second redundant column in the first redundant block to replace the second defective column when the second defective column is in the first block. The second set of CAM cells cause the fourth redundant column in the second redundant block to replace the second defective column when the second defective column is in the second block.

Nonvolatile memory with blocked redundant columns and corresponding

In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.

Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays

A noise filter to eliminate short, multiple pulses output from an address transition detection ('ATD') circuit caused by address line noise occurring during a read operation of a nonvolatile semiconductor memory. The ATD circuit includes a pulse summation circuit. Each address line sends an input pulse to the pulse summation circuit when the address bit corresponding to the address line changes. The pulse summation circuit adds and extends the input pulses to form output pulses. Pulse extension is performed by a delay chain formed by NAND and NOR gates. Each output pulse begins after a first predetermined time from the leading edge of an input pulse. The delay chain is set on the leading edge of each input pulse. The trailing edge of each input pulse determines when the delay chain will begin to reset. The extended pulse ends after a delay caused by the delay chain unless a subsequent pulse leading edge occurs within a second predetermined time from each trailing edge. In this way, short, multiple input pulses are turned into one long continuous output pulse. This prevents the sending of short pulses into sensing circuits where they would cause the wrong data to be sensed and latched.

Address transition detection noise filter in pulse summation circuit for

A circuit for providing reference voltages to be used by sense amplifiers of output circuitry of an integrated circuit memory array to allow the sense amplifiers to ascertain the values stored by memory cells of the array. The circuit includes a first branch which has transistor circuitry for establishing a reference current, a second branch of the circuit including a first transistor device and apparatus for mirroring the reference current through the first transistor device, and a plurality of output branches each connected to a sense amplifier to provide a reference voltage to be used by the sense amplifier. Each of the output branches includes a second transistor device with characteristics essentially identical to the characteristics of the first transistor device. Apparatus is included in the output branches for providing voltages at all terminals of the second transistor devices equal to the voltages at all terminals of the first transistor device so that the reference current through each of the second transistor devices is forced to be identical to that through the first transistor device. The second branch is replicated to increase current available and circuit speed.

High-speed bias-stabilized current-mirror referencing circuit for

A circuit to ensure that a flash memory device with a write state machine ('WSM') and address transition detection ('ATD') provides correct data after a write/erase step, after an erase suspend command is issued or when the device comes out of deep power-down mode. Whenever the WSM takes control of the device the ATD circuits are disabled. When the WSM relinquishes control over the read path it enables ATD by deasserting the disable ATD bar ('DATDB') signal. An internal signal that is a logical inversion of the chip enable bar ('CEB') input is used along with the DATDB signal to generate ATD pulses. Hence, if the user presents a valid address at the address pins with CEB held deasserted when entering the erase suspend mode, the deassertion of the DATDB by the WSM will generate an ATD pulse and valid data will be presented on output pads of the device after an access time. When the device enters the power-down mode, the ATD content addressable memory ('CAM') is powered-down to system power ('VCC') and all internal addresses are forced high. When the device comes out of the power-down mode, the DATDB signal toggles from high (logical one) to low (logical zero). This ensures that an ATD pulse is generated even if the addresses are not toggled.

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Folsom, CA, United States of America

Sachidanandan Sambandan