Infineon Technologies Ag

Sabine Kling

Dominique Savignac

Andreas Baenisch

Andreas B&auml;nisch

Helmut Schneider

Henning Haffner

Hans-Peter Moll

Athanasia Chrysostomides

Werner Obermaier

Elke Hietschold

Peter Pfefferl

Ines Anke

The invention relates to two methods for reading and two methods for storing data, and also to an apparatus for compressing data and decompressing data which are provided for storage by a computer system on a bulk memory of the random access type, which computer system provides the data for storage on a bulk memory on the basis of the rules of a file system, where the data are organized in data blocks, where the data blocks contain organization information for managing the data blocks and contain the user information which is to be stored, where cohesive user information areas can be distributed over a plurality of data blocks which are then concatenated to one another using their organization information.

Method for storing data, method for reading data, apparatus for storing data and apparatus for reading data

A data memory for storing data, having a memory cell array ( ), which comprises a large number of memory cells ( ), each of which can be addressed by means of a memory cell select transistor ( ) connected to a word line ( ) and to a bit line ( ) and which have a storage capacity for storing one data bit, the memory cell array ( ) containing redundant memory cells ( ), which are provided in order to replace memory cells ( ) which have been produced wrongly, by means of readdressing, and having read amplifiers ( ), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell ( ) via an associated bit line ( ) and are supplied with a buffered supply voltage, the redundant memory cells ( ) which have not been readdressed being connected to the associated bit lines ( ) and additionally buffering the supply voltage for the read amplifiers ( ).

Data memory with redundant memory cells used for buffering a supply voltage

The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair ( ), the binary memory cell signal from the memory tell is switched through via the bit line pair ( ) to at least one sense amplifier ( ), a binary output signal of the sense amplifier ( ) is switched through to a local data line pair ( ) as a binary intermediate signal, the binary intermediate signal on the local data line pair ( ) is switched through to at least one main data line pair ( ) by means of a main data line switching transistor pair ( ) in a manner dependent on a row control signal fed via a row control line ( ), the main data line switching transistor pair ( ) being arranged in the through-plating regions formed between the memory cell arrays.

Method and circuit arrangement for reading out and for storing binary memory cell signals

A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit structures and dummy circuit structures, whereby the dummy circuit structures which are smaller than a minimum structural size are joined to an additional second dummy circuit structure. The additional circuit structure is provided in such a way that the minimum structural size, which is determined by a smallest required joint surface of the photoresist on the substrate, is exceeded. A semiconductor circuit is also provided, which includes functional circuit structures and dummy circuit structures, the dummy circuit structures being joined to the additional dummy circuit structures.

Method for producing circuit structures on a semiconductor substrate and semiconductor configuration with functional circuit structures and dummy circuit structures

The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S D S D S ) arranged in parallel next to one another; a contact level (K ) with a respective plurality of contacts ( ) arranged regularly in the longitudinal direction of the individual strip-shaped regions (S D S D S ); the contacts ( ) being arranged in the widthwise direction of the individual strip-shaped regions (S D S D S ) in such a way that the widthwise extent of corresponding contacts ( ) of neighboring regions varies.

Integrated circuit with active regions having varying contact arrangements

An integrated semiconductor chip has at least two metal interconnects of two different metallization planes, which are disposed parallel to one another. The metal interconnects are connected to one another via at least one electrically conductive contact point. The metal interconnects, for each direction, run orthogonally with respect to one another in a first region. For each direction, they run parallel to one another and at an oblique angle to the directions of the metal interconnects of the first region in a second region ( ), in which they are contact-connected to one another. This configuration makes it possible, with little influence of electromigration, to have a comparatively small space requirement needed for the contact connection of mutually orthogonal interconnects.

Growing community of inventors

München, Germany

Sabine Kling