Intel Corporation

Qualcomm Incorporated

Sabine Francis

Alexander Gendler

Hanna Alam

Shadi T Khasawneh

Damian Maiorano

Tanvir Manhotra

Certain aspects provide a method of efficiently computing a starting address and offset for a memory prefetch address. The method generally includes computing a distance parameter that represents a difference between a line trigger virtual address and a producer virtual address, generating a starting address for a memory prefetch as a function of the distance parameter and a stride size, wherein the staring address is generated using a logically shifted version of the distance parameter if a first condition is met, and performing the memory prefetch using the generated starting address.

Efficient non-stalling cacheline triggered prefetch pipeline optimization for indirect memory accesses

In one embodiment, a processor includes: at least one configuration register to store configuration information for a hardware resource including a control circuit to configure the hardware resource based at least in part on the configuration information; a performance monitor to maintain performance information during execution of an application on the processor; and a controller coupled to the at least one configuration register. The controller may dynamically provide the configuration information to the at least one configuration register based at least in part on the performance information, and the control circuit is to adjust a performance tuning of the hardware resource according to the configuration information. Other embodiments are described and claimed.

System, apparatus and method for dynamically configuring one or more hardware resources of a processor

Growing community of inventors

Austin, TX, United States of America

Sabine Francis