Optimum Semiconductor Technologies Inc.

Sabin Daniel Iancu

C John Glossner

Paul Gerard D'Arcy

Gary J Nacer

Shenghong Wang

Arthur Joseph Hoane

Murugappan Senthilvelan

Vitaly Kalashnikov

Surducan Emanoil

Surducan Vasile

A monolithic dual band antenna is provided. The monolithic dual band antenna includes a first layer comprising a high frequency band antenna. The monolithic dual band antenna further includes a second layer underlying the first layer. The second layer includes a low frequency band antenna. The geometry of the high frequency antenna relative to the low frequency antenna causes resulting electric fields of the high frequency band antenna to be orthogonal to the resulting electric fields of the low frequency band antenna.

Monolithic dual band antenna

A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.

Method and apparatus for enabling a processor to generate pipeline control signals

A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.

Multithreading using an ordered list of hardware contexts

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Pleasantville, NY, United States of America

Sabin Daniel Iancu