Intel Corporation

Saad Monasa

Richard Edward Fackenthal

Ramkarthik Ganesan

Matthew G Dayley

Kiran Pangal

Kerry Dean Tedrow

Raymond W Zeng

Matthew Goldman

Rezaul Haque

Hemant P Rao

Quan H Ngo

Ahsanur Rahman

Mini Goel

Rouhollah Mousavi Iraei

Dung C Nguyen

A state may be encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

Encoding additional states in a three-dimensional crosspoint memory architecture

A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.

DDR flash implementation with direct register access to legacy flash functions

A Double Data Rate (DDR) nonvolatile memory includes a DDR I/F block to receive an address that is used to separate DDR data into coherent data and non-coherent data that are stored separately in the DDR nonvolatile memory.

DDR flash implementation with hybrid row buffers and direct access interface to legacy flash functions

A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.

Multi-level memory cell sensing

A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Multi-stage digital-to-analog converter

An interim density top boot flash memory architecture may be implemented by locking a portion or block of memory to prevent memory read and write accesses, thereby reducing the overall capacity of the memory. At the same time, this may be done without interfering with the access to parameters needed for implementing booting. In some embodiments, the locked memory may be placed at a block above the lowest addressable block that is accessed by an internal address.

Growing community of inventors

Sacramento, CA, United States of America

Saad Monasa