Hewlett-packard Company

Avago Technologies General IP (singapore) Pte. Ltd.

Palau Acquisition Corporation (delaware)

Hewlett-packard Development Company, L.p.

Agilent Technologies, Inc.

S Paul Tucker

Alan S Krech, Jr

Edmundo Rojas

Theodore G Rossin

Ted Scott Rakel

Jon L Ashburn

Glenn W Strunk

Michael S McGrath

Mercedes E Gil

Steven J Kommrusch

Venitha L Manter

Bradly J Foster

Kyle R Berry

A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory. The packet transfer request generator initiates a transfer request over a switch with a remote destination. While the request is processed, the packet checker verifies packet correctness and stores the packet data for transmission to the remote destination. If a packet is in error, a bad tag is set and the packet transfer is aborted.

Handling and discarding packets in a switching subnetwork

In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

Systems and methods for providing data packet flow control

A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.

Apparatus and methods for dynamic reallocation of virtual lane buffer space in an infiniband switch

An infiniband architecture switch, includes a plurality of ports each configured to receive switch parameters, identify at least one data-packet error condition responsive to the switch parameters, generate a trap-initialization signal when the at least one data-packet error condition matches a trap-error condition, and a switch manager configured to receive the trap-initialization signal. A method for generating a switch manager control signal includes identifying at least one data-packet error condition in an infiniband architecture switch, determining when the at least one data-packet error condition matches a trap-error condition, generating a trap-initialization signal responsive to the trap-error condition, and forwarding the trap-initialization signal to a switch manager.

Switch-management agent trap scheme in an infiniband-architecture switch

Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.

Method and apparatus for ascertaining and selectively requesting displayed data in a computer graphics system

A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.

Apparatus and methods for combinational error detection in an InfiniBand switch

A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor. Further, the system includes a fog blending unit responsive to the color value and the fog blending factor for each pixel of the primitive and also to a fog color value, that blends the fog color value with the color value for each pixel of the primitive according to the fog blending factor for the respective pixel, and that provides a fogged color value for each pixel of the primitive. In addition, the computer graphics system may include a first interpolator, responsive to the color value and the cooked exponent value for at least one pixel of the primitive, that determines the color value and the cooked exponent value along an edge of the primitive so as to provide the cooked exponent value and the color value for each pixel of the edge of the primitive. Further, the computer graphics system may also include a second interpolator, responsive to the cooked exponent value and the color value for each pixel of the edge of the primitive, that determines the cooked exponent value and the color value along a span of the primitive so as to provide the cooked exponent value and the color value for each pixel of the span of the primitive. In this way, the system provides fast and accurate exponential and exponential-squared fog blending of the color values of the primitive without a lot of hardware.

Computer graphics system having per pixel fog blending

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

ROM-based control unit in a geometry accelerator for a computer graphics system

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. Finally, a branch central intelligence mechanism controls branching between the control units by defining the next address field.

Centralized branch intelligence system and method for a geometry accelerator

A system and method computes the color of a plurality of vertices of one or more graphic primitives in a graphics accelerator. The method includes the steps of receiving lighting properties of a primitive vertex and determining whether predetermined lighting properties of the vertex are the same as a previously computed vertex. If predetermined lighting properties are the same as the previously computed vertex, then the method retrieves at least one preprocessed value from a storage location; and utilizes the at least one preprocessed value to compute the vertex color. If, however, the predetermined lighting properties are not the same as the previously computed vertex, then the method computes at least one preprocessed value from the received lighting properties of the primitive vertex, stores the at least one computed preprocessed value in a storage location, and utilizes the at least one preprocessed value to compute the vertex color. The system includes at least one processing unit (e.g., ALU) for performing mathematical operations on lighting properties of a vertex of a graphics primitive. It also includes a storage area for storing predetermined values processed by the processing unit. A receiver is included and configured to receive at least two lighting properties defining a primitive vertex, and a lighting property comparator is configured to compare the at least two lighting properties with previously received lighting properties to determine whether they are the same. Finally a controller is provided and adapted to control the storage and retrieval of values from the storage area and the processing unit, the controller including storage control means responsive to the lighting property comparator configured to save newly processed vertex color values in the operational storage register and to retrieve preprocessed values from the storage area.

Graphics accelerator with improved lighting processor

ROM-based control units in a geometry accelerator for a computer

A novel system and method computes a floating point value of an exponential expression in the form of 'a.sup.x ' in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving the values 'a' and x of the exponential expression, where both 'a' and x are represented in floating point format. As will be appreciated by those skilled in the art, the values will by supplied by software through an appropriate graphics application program interface (API). The method utilizes a mantissa value of the floating point representation of 'a' to index a first value in a first look-up table, the value being an approximation for log2(a). Then, the method multiplies the looked-up value by the value of x to obtain an intermediate result. This intermediate result is then partitioned into a fractional component and an integer component, wherein the fractional component is normalized/converted to floating point format. The method then utilizes a mantissa value of the floating point representation of the fractional component of the intermediate result to index a first value in a second look-up table, the value being an approximation for 2.sup.fract, where fract is the fractional component. Thereafter, the method computing 2.sup.integer, where integer is the integer component. This step may be directly computed by the math core of the geometry accelerator, since it is an integer exponent. Finally, the method multiplies the results of steps that compute the 2.sup.fract and 2.sup.integer values to obtain a final value. This final value is a close approximation of the exponential expression a.sup.x.

System and method for calculating floating point exponential values in a

A method computes exponentials of a lighting equation in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving values for a first term 'a' and a second term 'x' of an exponential in the form a.sup.x. The method then evaluates at least one of the first and second terms to determine whether it is an integer value. If the evaluating step determines that the at least one of the terms is an integer value, then the method sets a bit in a memory location. Thereafter, the method examines a bit in the memory location. If the bit is set, then the invention executes an integer exponentiation routine to calculate a.sup.x directly in the math core. If, however, the bit is not set, then the invention executes a floating point exponentiation routine to closely approximate the calculation of a.sup.x.

System and method for conditionally calculating exponential values in a

The present invention provides a method and apparatus for processing primitives in a computer graphics display system. The present invention comprises a geometry accelerator for processing polygons to provide two-sided lighting for front and back facing polygons. The geometry accelerator comprises a lighting machine and a memory device in communication with the lighting machine. The geometry accelerator receives command data, vertex data, and parameter data from a central processing unit (CPU) of a computer graphics display system. The vertex data comprises polygon vertex color data, vertex coordinate data and vertex normal data. The parameter data comprises front and back material parameters. The command data comprises information relating to the type of primitive to be processed by the lighting machine. The geometry accelerator looks at the command data to determine whether the polygon is a front or back facing polygon and informs the lighting machine as to whether the polygon is a front or back facing polygon. The lighting machine will then fetch the correct set of material parameters and use them to calculate lighting.

Growing community of inventors

Ft. Collins, CO, United States of America

S Paul Tucker