Integrated Device Technology, Inc.

S K Lee

Chuen-Der Lien

Guo-Qiang Lo

Chih-Hsiang Chen

Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate structures over a semiconductor substrate. A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack having a sidewall is formed over the gate dielectric layer. The gate stack comprises a conductive layer and a capping nitride layer overlying the conductive layer A liner is selectively deposited over the gate stack such that the liner is deposited on the capping nitride layer at a rate lower than the rate of deposition on the conductive layer Thus, the liner is substantially thinner on the capping nitride layer than on the conductive layer A nitride spacer is formed over the liner A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks and substantially free of voids.

Gate structures having sidewall spacers using selective deposition and method of forming the same

A first insulating layer ( ) overlying semiconductor substrate ( ) has a plurality of conductive paths ( ) disposed thereon. Each of the plurality of conductive paths has at least a major portion thereof overlied with a second insulating layer ( ). A third insulating layer ( ), having air gap ports ( ) formed therein, overlies adjacent conductive paths and extends from one to another such that an air gap ( ) is formed. A passivation layer ( ) overlies third insulating layer and seals the plurality of air gaps ports to form an insulation structure ( ) for a semiconductor integrated circuit, and method thereof.

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Hillsboro, OR, United States of America

S K Lee