Advanced Micro Devices Corporation

S Doug Ray

James F Buller

Mark Brandon Fuselier

Edward E Ehrichs

Chad Weintraub

Craig M Peterson

A method for asymmetric spacer formation integratable into a manufacturing process for integrated circuit semiconductor devices is presented. The method comprises forming a gate structure over a substrate, and forming a sidewall layer overlying the gate structure and substrate, wherein the sidewall layer comprises a first portion overlying a first sidewall of the gate structure. A photoresist structure is formed adjacent to the first portion, and subjected to an ion beam. The photoresist structure serves to shield at least part of the first portion from the ion beam. During irradiation, the wafer is oriented such that a non-orthogonal tilt angle exists between a path of the ion beam and a surface of the first sidewall. Formation of asymmetric spacers is possible because radiation damage to unshielded sidewall portions permits subsequent etches to proceed at a faster rate.

Method for asymmetric spacer formation

A method and apparatus for evaluating the performance degradation of semiconductor integrated circuit devices due to hot carrier injection (HCI) is implemented. A device under test (DUT) is subject to a sequence of stress cycles. A stress condition is set on the device, for example, an over voltage condition may be applied as the operating voltage of the device. A physical parameter serving as a measure of device performance, for example, the case temperature of the device, is then characterized by varying the physical measure as the DUT executes benchmark cycles until the device fails. Benchmark cycles may be run using conventional benchmark software, or, alternatively, synthetic code. Extrapolation of the data to nominal operating conditions provides a characterization of the expected lifetime of the DUT due to HCI.

Apparatus to evaluate hot carrier injection performance degradation and method therefor

A device and method is provided for programming an output logic level based on one or more revisions to mask layers utilized for forming an integrated circuit. The programmed logic level is represented as a logic value and is output from a device embodied within the integrated circuit formed from the mask layers. Each revision of mask layers is represented as a binary value at bit locations within a revision code output from the present system. The device and method hereof is used to program the system in accordance with an infinite numbers of mask layers and revisions to those mask layers. The programmed output from the system is represented as a revision code of numerous bits output through a pin location extending from the outer surface of a package surrounding the integrated circuit. Ready access to the pin location allows an end user to access and determine a version of integrated circuit product embodied within a sealed package, without opening the package and destroying the enclosed product.

Device and method for programming a logic level within an integrated

Device and method for programming a logic level within an intergrated

An improved power-on reset circuit is provided for controlling reset signal transition until after the power supply has achieved operational levels. Specifically, the reset signal is designated to transition from a high to a low state after the power supply exceeds a fixed reference voltage. The reference voltage is set at a voltage value greater than the operational voltage level of devices within a load circuit connected to the output of the power-on reset circuit. The power-on reset circuit includes numerous subcircuits used to define the reference voltage, trigger the reference voltage in relation to the power supply voltage, delay the triggered voltage, and buffer the delayed, triggered voltage to a reset value capable of driving load circuit impedances.

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Austin, TX, United States of America

S Doug Ray