Hewlett-packard Development Company, L.P.

Hewlett-packard Company

S Brandon Keller

Gregory Dennis Rogers

George Harold Robbert

Charles A Lelm

A system, method and software product achieve analysis capacity for circuit analysis tools. One or more stages of a circuit design are identified. One or more descriptions of the stages are stored. Stage results are generated by independently analyzing each stage based upon the descriptions. Stage results from analyzed stages are combined to produce a single result set for the circuit design.

System and method for achieving analysis capacity for circuit analysis tools

A system, method and software product determine detail of analysis in a circuit design. Pull-up driver transistors of at least one stage of the circuit design are identified. Pull-down driver transistors of the stage are identified. Configuration commands associated with control signals of the pull-up and pull-down driver transistors are processed to determine if the pull-up driver transistors and pull-down driver transistors are tied on or tied off. A determination is made whether the stage has drive fight and switching current. A detailed analysis is performed of the stage of the stage has drive fight or switching current.

System and method for determining detail of analysis in a circuit design

A method for controlling analysis by an analysis tool of multiple instantiations of a circuit in a hierarchical circuit design is described. The method comprises providing a user-selected analysis option to the analysis tool; analyzing a first instantiation of the circuit as specified by the analysis option; and responsive to the first instantiation of the circuit passing the analysis, terminating analysis of the circuit.

System and method for controlling analysis of multiple instantiations of circuits in hierarchical VLSI circuit designs

A system, method and software product processes configuration information. One or more configuration elements are identified from one or more configuration commands and associated with design elements of an electronic circuit design. Each configuration element is retrieved for at least one design element.

System and method for processing configuration information

Systems, methods and software products determine activity factors of a circuit design. An activity factor is assigned to one or more node types. One or more signal nets from a netlist of the circuit design are read. The signal nets are processed to associate one of the node types with each of the signal nets. An activity factor is determined for each of the signal nets based upon node type.

Systems and methods for determining activity factors of a circuit design

A system and method for determining unmatched design elements in a circuit. The system determines instances of a first type and a second type of the design elements that are connected to a specific node in the circuit, and stores the gate signal name for each determined said occurrence of the first type of design element in a first list. The gate signal name for each determined said occurrence of the second type of design element is than stored in a second list. A value of a design element characteristic and indicia thereof for each determined said occurrence of the first and the second types of the design elements is than stored. A set difference operation is preformed on the first list and the second list to determine orphan gate signal names that appear in only one said list; and a cumulative value is determined for each said design element characteristic, by adding the design element characteristic value corresponding to each stored said orphan gate signal name, to produce a total design element characteristic value.

System and method for determining unmatched design elements in a computer-automated design

Systems, methods, and software products determine a highest level signal name in a hierarchical circuit design. A signal path is traced into a hierarchically lower level of the circuit design from a predetermined net in the circuit design to a predetermined terminal instance, while adding indicia, to an instance history list, of each subsequent instance encountered. A port instance is determined on the terminal instance associated with a selected net for which the highest level signal name is to be determined. The selected net is designated as the current net. For each stored indicia in the instance history list, the net connected to the current net in a hierarchical parent of the instance identified by the indicia is determined, to establish a next current net. If a condition exists wherein there is no connection from the current net to a hierarchically higher level instance, then the current net is established as the highest level signal name for the selected net.

System and method for determining a highest level signal name in a hierarchical VLSI design

Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.

Computer aided design systems and methods with reduced memory utilization

Systems, methods, software products utilize fast analysis information during detailed analysis of a circuit design. One or more design blocks of the circuit design are electronically analyzed to determine fast analysis results based upon assumptions of ported signal nets of each one of the design blocks. Next, it is determined whether hierarchical signal net connectivity of block instances of the design blocks and the assumptions match. If the hierarchical signal net connectivity matches the assumptions, the fast analysis results are utilized to generate detailed analysis results. If the hierarchical signal net connectivity does not match the assumptions, the one or more blocks in the hierarchical signal net connection are electronically analyzed to generate detailed analysis results.

Systems and methods utilizing fast analysis information during detailed analysis of a circuit design

A method and system for determining wire capacitance for a VLSI circuit design, comprising determining all hierarchical blocks of a portion of the design; storing, for a plurality of the blocks, indicia of the most accurate one of a plurality of wire capacitance data sources; generating a wire capacitance database with an entry for each net in at least a plurality of the blocks, using information stored in at least one of the wire capacitance data sources; generating a hierarchical connectivity model for the design; and using the hierarchical connectivity model and said wire capacitance database to determine a cumulative wire capacitance value for each HLSN in each of the blocks in a portion of the design to be analyzed.

System and method for determining wire capacitance for a VLSI circuit

Systems, methods, and software products iteratively traverse a hierarchical circuit design. An initial net and an instance history that uniquely defines the initial net within the design are selected. The initial net and the instance history are appended to a list of nets to be processed. The initial net and the instance history are inserted into a set of visited nets. Each additional net connected to the initial net is visited in response to a first request from a user. The initial net and each additional net are returned in response to a second request from the user.

System and method for iteratively traversing a hierarchical circuit design

A method for controlling activity of a temporary file associated with a target file to which data is to be written.

System and method for controlling activity of temporary files in a computer system

A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, that includes the steps of selecting an output node from the netlist, preparing the predefined logic equation for searching FETs in the netlist, and identifying FETs from the netlist that are implemented in the prepared predefined logic equation.

Method and system for identifying FETs implemented in a predefined logic equation

A method is disclosed for analyzing a VLSI circuit design stored in a computer system. Each segment of the design layout is stored in the computer memory for analysis and implementation. An electronic computer-aided design (E-CAD) program is used to analyze the design. First, the E-CAD tool is run on the entire design or on a designated part thereof. The tool compares the design to specifications and returns a list of violations on a segment basis. The E-CAD tool identifies violations for the designer to fix through redesign or clarification of specifications. The method marks or flags signals of those segments reporting violations. After the designer has attempted to remedy the violations, the method reruns the E-CAD analysis on those signals that reported a violation during a prior run.

Method and system for analyzing a VLSI circuit design

A method is disclosed for identifying FETs that comprise NAND and NOR logic gates in a circuit design having numerous FETs. A potential logic gate output node is queried to determine the configuration of FETs around the output node. FETs connected directly between the output node and either a high or low potential (VDD or GND) are identified and stored to memory along with a their corresponding gate signals. Branch FETs that are of a different type than the directly-connected FETs and that are channel-connected between the output node and either VDD or GND are also identified. If a gate signal for each FET in a branch corresponds to a gate signal of a directly-connected FET at the same output node, then a logic gate exists.

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Evans, CO, United States of America

S Brandon Keller