Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Ryuuji Shibata

Isamu Kobayashi

Toshifumi Takeda

Youichi Matsumoto

Satoshi Meguro

Kouichi Nagasawa

Masahiro Ogata

Hisahiro Moriuchi

Kikuo Sakai

Hideo Meguro

Kouki Noguchi

Kazuhiko Iwasaki

Mitsuru Akizawa

Noboru Yamaguchi

Ken Uchida

A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.

Semiconductor memory device with data error compensation

MISFET's are formed in the depletion mode in advance. MISFET's which are selected from these depletion-mode MISFET's are then formed into enhancement-mode or weak depletion-mode MISFET's to thereby write desired data into the memory cells of a read-only memory. The change of the MISFET's from the depletion mode into the enhancement mode (or weak depletion mode) is effected by introducing an impurity into the channel regions of the selected MISFET's in a manufacturing step that is carried out after the formation of the gate electrodes of the MISFET's.

Process for producing ROM

MISFET's are formed in the depletion mode in advance in a process comprising blanket implantation of the region in which memory cells are to be formed. MISFET's which are selected from these depletion-mode MISFET's are then formed into enhancement-mode or weak depletion-mode MISFET's to thereby write desired data into the memory cells of a read-only memory. The change of the MISFET's from the depletion mode into the enhancement mode (or weak depletion mode) is effected by introducing an impurity into the channel regions of the selected MISFET's in a manufacturing step that is carried out after the formation of the gate electrodes of the MISFET's.

ROM and process for producing the same

Disclosed in an N-type MISFET having the LDD structure in which the short-channel effect is reduced by employing arsenic, which has a smaller diffusion coefficient value than that of phosphorus, to form low- and high-impurity concentration regions which constitute in combination source and drain regions of the MISFET.

Semiconductor integrated circuit device with MISFETS using two drain

A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.

Read-only memory

Growing community of inventors

Higashiyamato, Japan

Ryuuji Shibata