Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Ryutaro Yamanaka

Hidetoshi Suzuki

Minoru Okamoto

Hideyuki Kabuo

Kevin Mark Stone

Tetsuya Ikeda

Yukihiro Sasagawa

Toshihiro Ishikawa

Kazuhiro Okabayashi

Kazufumi Tanoue

Noriaki Minamida

A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

Panel control device and panel control system

A communication terminal apparatus wherein even in a case of occurrence of a compressed mode, an evaluation can be performed by a detecting function to select an appropriate TFC (TRANS Format Combination). In this communication terminal apparatus, upon occurrence of a compressed mode, a compressed mode information generating part () outputs both a gap section and a gap start slot number for application to a transmission power determining part (), which then counts the slots in which the TFC transmission power exceeds an upper limit for each TFC. At this moment, the transmission power determining part () replaces the TFC transmission power, for the slots of the gap section, by the TFC transmission power of the slots other than those of the gap section. ATFC status managing part () determines, based on the counting result of the transmission power determining part (), the status of each TFC.

Communication terminal apparatus

Digital signal processing sectionhas reconfigurable device, and reconfigurable deviceconfigures decoding sectionand coding sectionby programming data. Decoding sectionacquires synchronization from a signal output from reception section, and demodulates and decodes the signal. CPUdownloads programming data of another radio communication system to store in storage sectionvia general bus. Further, CPUreads out the stored programming data, and reconfigures reconfigurable device. Storage sectionstores the programming data.

Communication apparatus and method for reconfiguring communication apparatus

A compressed mode outbound propagation path quality information transmitting method and an outbound propagation path quality information transmitting apparatus are disclosed that enable a mobile station to maintain reception performance virtually equal to that of a conventional compressed mode outbound propagation path quality information transmitting method, and enable operation control relating to received signal measurement and so forth necessary for generating outbound propagation path quality information transmitted on an uplink to be performed easily. Provision is made so that, in compressed mode in which transmission gap intervals appear in both a downlink and uplink, a mobile station does not carry over outbound propagation path quality information generated based on a received signal preceding the beginning of that downlink transmission gap interval until that downlink transmission gap interval and uplink transmission gap interval both end.

Method and apparatus for transmitting downstream propagation path quality information in compressed mode

A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Communications digital signal processor and digital signal processing method

A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register&#x2014;register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.

Processing unit and processing method

Counter control sectionincrements a row number and column number on a two-dimensional array for a block interleave expressed by a matrix two-dimensional array, outputs the incremented numbers as the read address values, bit inversion apparatusperforms bit inversion using the read address values as inputs, column conversion sectionoutputs the address values corresponding to the bit inversion output values and the column numbers from counter control sectionas the column conversion values, shift registerbit-shifts the output values of bit inversion apparatusand outputs as the address offset values, adderadds up the address offset values and column conversion values and size comparison sectioncompares the addition value with the interleave size and outputs data which is not greater than the interleave size as address values.

Interleave address generation device and interleave address generation method

A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM and PM of an old state is added to each branch metric BM and BM separately. A path metric of a new state N is formed by comparing the value of PM &plus;BM to the value of PM &plus;BM . A path metric of a new state N&plus;2 is formed by comparing the value of PM &plus;BM to PM &plus;BM

Two path metrics (PM,, PM,) are read from path metric storing means,, and two path metrics (BM,, BM,) are read from branch metric storing means,. An ACS operation is executed using PM,&plus;MB,and PM,&plus;BM,by comparing means,, adding means,, comparison result storing means,, and selecting means,. In parallel with the ACS operation, an ACS operation is executed using PM,&plus;MB,and PM,&plus;BM,by comparing means,, adding means,, comparison result storing means,, and selecting means

Processor and processing method

In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result. In this case, at least two digits are set before the decimal point, thereby allowing each of the products of the high-order word/low-order word of the double-precision multiplicand and the high-order word/low-order word of the double-precision multiplier, to be obtained at a bit width which is larger by at least one bit than a bit width of double precision.

Computing apparatus for double-precision multiplication

The error correction device is provided with an internal code decoder which outputs a series of decoded data and reliability information of the decoded data, a CRC (Cyclic Redundancy Check) decoder, a de-interleaver, an erasure position detector, and an external code decoder for decoding an external code by soft judgement. When the external code is decoded by the soft judgment, not only the series of decoded data of the internal code and their reliability information but also frame error information based on CRC are used as input signals. It is therefore possible to perform error correction with a high accuracy and to obtain low BER characteristics.

Growing community of inventors

Yokohama, Japan

Ryutaro Yamanaka