Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Ryuta Inobe

Motohiro Maeda

Masakazu Matsuura

Masayuki Ooki

A solid-state imaging device according to an embodiment includes a first charge detector, a first output circuit and a pulse generator. The first charge detector includes a plurality of first pixels and is configured to detect charges accumulated in the plurality of first pixels. The first output circuit is configured to amplify the charges detected by the first charge detector and output the charges as an output signal. The pulse generator is configured to generate a sampling pulse to extract a charge signal from the output signal during a period different from a signal output period in which the output signal is outputted.

Solid-state imaging device

An imaging device includes a semiconductor substrate, pixels, a charge detector, charge storage portions, an output gate portion and a shift gate portion. The pixels and the charge detector are provided in the semiconductor substrate. The charge storage portions are provided on the charge detector side of the pixels, and linked to the pixels. The output gate portion is positioned between the charge detector and the charge storage portions, and includes charge transfer channels extending in a radial configuration in directions from the charge detector toward the pixels. The shift gate portion is positioned between one charge storage portion and one charge transfer channel. The shift gate portion includes a gate electrode provided on the semiconductor substrate. A planar configuration of the gate electrode has a side orthogonal to the extending direction of the one charge transfer channels, the side being most proximal to the one charge transfer channel.

Imaging device

An aspect of one present embodiment, there is provided a solid state image processer, including a sample-and-hold circuit sampling an output signal of the CCD to hold the output signal of the CCD as voltage, a pre-buffer receiving an output signal of the sample-and-hold circuit, a selection circuit receiving the output signal of the pre-buffer as a first input signal and the output signal of the CCD as a second input signal to select the first input signal or the second input signal as an output signal of the selection circuit according to an instruction of a selection signal, and a main buffer receiving the output signal of the selection circuit.

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Fujisawa, Japan

Ryuta Inobe