Hitachi, Ltd.

Ryusuke Sahara

Mitsugu Kusunoki

Kazutaka Mori

Hiroshige Kogayu

Kozaburo Kurita

Hideki Sakakibara

Atsushi Okumura

Yuuji Suzuki

A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.

Operational amplifier

A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

Semiconductor device having D/A conversion portion

A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.

Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode

The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

Growing community of inventors

Ome, Japan

Ryusuke Sahara