Eudyna Devices Inc.

Ryuji Yamabi

Yoshihiro Yoneda

Hiroshi Yano

A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.

Method of making PIN-type photo detecting element with a controlled thickness of window semiconductor layer

An optical semiconductor module with a light receiving element with an upper and side light receiving face and a light emitting element mounted on the same mounting carrier. The light receiving element has a light receiving face on an upper face and a side face covered with an antireflection film. The mounting unit has the light emitting element and the light receiving element mounted so that they encompass a positional relationship that the light emitted from the light emitting element is optically connected at least on the light receiving face of the side face of the light receiving element.

Light receiving element with upper and side light receiving faces and an optical semiconductor module with the light receiving element and a light emitting element mounted on the same mounting unit

PIN-type photo detecting element with three semiconductor layers, and window semiconductor layer having controlled thickness

A semiconductor device has an electrode pad, a capacitor and a substrate. The substrate has a given area on which the electrode pad and the capacitor are arranged. The electrode pad and the capacitor are arranged on the substrate so that each of at least two sides of the capacitor and each of at least two sides of the electrode pad is adjacent to each other at a given interval. The capacitor has a connecting side that connects the two sides of the capacitor and faces to the electrode pad. Outside angles of the capacitor formed by the connecting side and the two sides of the capacitor are more than 90 degrees.

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Yamanashi, Japan

Ryuji Yamabi