Fujitsu Corporation

Fujitsu Vlsi Limited

Ryuji Tanaka

Tetsuhiko Endoh

Yoshihiro Takemae

Hiroaki Watanabe

Masaki Kirinaka

Hirosuke Komyoji

Masaru Masuyama

Katsuhiko Itakura

A semiconductor memory includes a memory having a plurality of input/output terminals for inputting/outputting parallel data: a parallel/serial conversion circuit connected to said parallel terminals of said memory so as to convert said parallel data of said memory into serial data and input/output the serial data; a plurality of test terminals connected to said parallel terminals of said memory, respectively; and a switch control circuit arranged between said parallel terminals of said memory and said parallel/serial conversion circuit, for disabling said parallel/serial conversion circuit.

Semiconductor memory device

An interface between a card-type peripheral device and a host machine, such as a PC, determines the operational supply voltage required to operate the peripheral device prior to the host machine supplying the operational supply voltage to the peripheral device. The host machine first receives information stored on the peripheral device specifying the operational voltage required to operate the peripheral device. The host machine then generates the proper operational supply voltage and provides it to the peripheral device. The interface prevents damage to the peripheral device due to the host machine supplying an incorrect operational voltage.

Host machine interface for reading information stored in peripheral card

A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal, a memory part having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal for receiving an address signal, a first input terminal for receiving a first chip select signal which selects a first byte, a second input terminal for receiving a second chip select signal which selects a second byte, and a decoder circuit for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.

Memory card

Growing community of inventors

Kawasaki, Japan

Ryuji Tanaka