Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Ultramemory Inc.

Micron Technology Incorporated

Ryuji Takishita

Hideyuki Yoko

Hiroki Fujisawa

Chikara Kondo

Naohisa Nishioka

Koji Kuroki

Takao Adachi

Akira Ide

Kazutaka Miyano

Takeshi Konno

Kentaro Hara

Yasutoshi Yamada

Tetsuaki Okahiro

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor moduleis provided with: a logic chip; a pair of RAM unitseach composed of a lamination-type RAM module; a first interposerelectrically connected to the logic chip and to each of the pair of RAM units; and a connection unitthat communicatively connects the logic chip and each of the pair of RAM units, wherein one RAM unitis placed on the first interposer, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unittherebetween, and the other RAM unitis disposed so as to overlap the one RAM unitwith the connection unittherebetween, and is also disposed along the outer periphery of the logic chip.

Semiconductor module

The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.

Semiconductor storage device

An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out from the memory cell. The sense amplifier is operated in a first mode with a first power source voltage difference and operated in a second mode with a second power source voltage difference smaller than the first power source voltage difference.

Semiconductor memory device having sense amplifier

A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.

Semiconductor memory device, method of adjusting the same and information processing system including the same

A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.

Semiconductor device

In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.

Semiconductor apparatus

To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

Semiconductor device semiconductor device testing method, and data processing system

In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG.).

Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

Semiconductor device having plural semiconductor chips laminated to each other

A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK, a synthesizing circuit that synthesizes outputs of these delay adjusting circuits to generate an internal clock signal, and supplies the internal clock signal to a real path, a clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path, and a clock driver that receives the output of the second delay adjusting circuit. These clock drivers have substantially the same circuit configuration. Accordingly, even when the power supply voltage fluctuates, influences of the fluctuations on the respective frequency-divided signals are almost equal. Thus, deterioration of the function of the DLL circuit due to fluctuations of the power supply voltage can be prevented.

DLL circuit and semiconductor device including the same

A delay amount variable circuit () adapted to change a delay amount according to a ZQ calibration result is inserted in a path of a DQ replica system. The delay amount of the path of the DQ replica system is variable and is adjusted so as to make constant a timing skew difference between a DQ buffer system and the DQ replica system. The ZQ calibration result changes depending on variations in temperature, voltage, and manufacture. Therefore, by obtaining the delay amount corresponding to these variations, there are obtained a DLL circuit with high accuracy that can make the skew difference constant, and a semiconductor device incorporating such a DLL circuit.

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Tokyo, Japan

Ryuji Takishita