Fujitsu Corporation

Fuji Electric Co., Ltd.

Fujitsu Microelectronics Limited

Ryuji Shimizu

Hideaki Konishi

Ryuji Yamada

Satoshi Masuda

Koji Kawaguchi

Naofumi Kobayashi

Masahito Suzuki

Kazuaki Mino

Hitoshi Watanabe

Koichi Itaya

Toshihito Shimizu

Junko Kumagai

Osamu Ōkano

Kazuyuki Yamamura

Naoko Karasawa

Takeshi Doi

Hirokazu Kadoi

Daisuke Tsukuda

Masayasu Hojo

Haruhiko Abe

Yuko Katoh

An uninterruptible power supply apparatus includes a power supply unit converting AC power to generate a DC voltage to be supplied to a loading device. The uninterruptible power supply apparatus further includes a first battery unit connected to the power supply unit to receive a DC current therefrom, and stores first DC power generated from the DC voltage. The first battery unit generates a DC voltage to be supplied to the loading device from the first DC power. The uninterruptible power supply apparatus includes a second battery unit connected in parallel to the power supply unit and stores second DC power, and generates, from the second DC power stored in the second battery unit, a DC voltage to be supplied to the loading device. The uninterruptible power supply apparatus further includes a controller for controlling operation of the power supply unit, the first battery unit and the second battery unit.

Uninterruptible power supply apparatus

In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

Delay failure test circuit

A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

Method and apparatus for supporting designing of LSI, and computer product

A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.

Built-in self-test circuit

Timing verification of the LSI test data is performed as follows. In test synthesis, a script text for static timing analysis (STA) is generated together with a test circuit. The STA script text is used to perform static timing analysis. Function verification is performed between a netlist generated through the test synthesis and a timing-verified netlist based on the static timing analysis. The function-verified netlist is released to a production division, and the netlist is used to automatically generate a test pattern by an automatic test pattern generation (ATPG) tool. A netlist comprising test vectors for automatic test equipment is acquired from the generated ATPG pattern.

Method of and apparatus for timing verification of LSI test data and computer product

The outputs of selectors to N are respectively connected to the data inputs DI to DIN of a RAM A. One inputs of selectors to N are respectively connected to the data outputs DO to DON of the RAM A, the other inputs are connected to corresponding outputs of the selectors to N. The outputs of the selectors to N are connected to data inputs D of respective scan flip-flops to N. Not in a RAM test mode, data input lines to N are selected by the selectors to N to provide to the data inputs DI to DIN of the RAM A and to the scan flip-flops to N through the selectors to N, respectively.

RAM functional test facilitation circuit with reduced scale

Growing community of inventors

Kawasaki, Japan

Ryuji Shimizu