International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Ryuji Orita

Sumeet Kochar

Malcolm Scott Ware

Freeman Leigh Rawson, Iii

Charles Robert Lefurgy

Wesley Michael Felter

Thomas M Brey

Mehul M Shah

Barry Alan Kritt

Patrick M Bland

Shiva R Dasari

Wingcheung Tam

Sudhir Dhawan

Timothy M Wiwel

Brian David Allison

Mark A Brandyberry

Karen April Taylor

Charles David Bauman

Susumu Arai

Robert H Bass

Sean P Brogan

Susumi Arai

Edward R Holley, Iii

Koichi Kii

Christopher C Ruggles

Jeremy K Holland

In a method for ejecting a plurality of hot plug slots sharing a power controller, a processor receives a request to eject a plurality of hot plug slots, wherein the plurality of hot plug slots share a power controller and have at least two adapters present. A processor causes an OS to incrementally eject the at least two adapters, wherein ejecting an adapter comprises the OS stopping at least one driver of the adapter, and the OS generating a request to remove power from a hot plug slot. Responsive to a request by the OS to remove power from a hot plug slot, a processor generates a signal that prevents the OS from recognizing the adapter is present in the hot plug slot. Responsive to all device drivers for the at least two adapters being stopped, a processor causes power to be removed from the plurality of hot plug slots.

Hot removing an I/O module with multiple hot plug slots

Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state ('p-state') of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

Managing power consumption of a computer

A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.

Debugging module to load error decoding logic from firmware and to execute logic in response to an error

Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state ('p-state') for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.

The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.

Persisting value relevant to debugging of computer system during reset of computer system

A method and apparatus are provided for thermal management of a multiprocessor computer system. The temperatures of the various processors within a multiprocessor system are monitored. When a processor is identified as overheated, a dummy process will be assigned to it, causing all other processes to be put on hold, thereby reducing the heat output of that processor. When the temperature of the processor lowers below another predetermined value, then the dummy process is terminated.

Thermal management of a multi-processor computer system

Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Directing interrupts to currently idle processors

A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.

System and method for using hot plug configuration for PCI error recovery

A facility is provided for hotplugging multiple adapters into a system having a bus with a plurality of adapter receiving hotplug slots. The facility includes connecting multiple hotplug adapters to multiple hotplug slots of the bus, and automatically determining a bus speed for the bus that the multiple hotplug slots and the multiple hotplug adapters connected thereto support. The automatically determining is transparent to a user of the system making the hotplug adapter connections and is independent of an order of connection of the multiple hotplug adapters to the multiple hotplug slots.

Method, system and program product for facilitating hotplugging of multiple adapters into a system bus and transparently optimizing configuration of the system bus

Growing community of inventors

Redmond, WA, United States of America

Ryuji Orita