Kabushiki Kaisha Toshiba

Ryuji Ohba

Ken Uchida

Junji Koga

Shinobu Fujita

Yoshio Ozawa

Mari Matsumoto

Tetsuya Kai

Shinichi Yasuda

Daisuke Matsushita

Kazuya Ohuchi

Tomohisa Mizuno

Makoto Yoshimi

Akira Toriumi

A memory device according to one embodiment includes a first interconnection, a second interconnection, a charge storage portion provided between the first interconnection and the second interconnection, a tunnel film provided between the first interconnection and the charge storage portion, and a block film. the charge storage portion is capable of accumulating an electron. The tunnel film includes a fine particulate layer that including conductive fine particulates satisfying the Coulomb blockade condition, a first tunnel insulating layer provided between the first interconnection and the fine particulate layer, and a second tunnel insulating layer provided between the fine particulate layer and the charge storage portion. The block film is provided between the charge storage portion and the second interconnection. The block film has an energy structure in which no concave portion with an energy barrier lower than energy barriers on both sides thereof is present.

Memory device

According to one embodiment, a memory device includes the following structure. A first double tunnel junction structure includes a first nanocrystal layer that includes first conductive minute particles, and first and second tunnel insulating films arranged to sandwich the first nanocrystal layer. A second double tunnel junction structure includes a second nanocrystal layer that includes second conductive minute particles, and third and fourth tunnel insulating films arranged to sandwich the second nanocrystal layer. A charge storage layer is arranged between the first and second double tunnel junction structures. First and second conductive layers are arranged to sandwich the first double tunnel junction structure, the charge storage layer, and the second double tunnel junction structure. The first conductive minute particles has an average grain size which is different from that of the second conductive minute particles.

According to one embodiment, a device includes a fin type active area on a semiconductor substrate, the active area having an upper surface with a taper shape, having a width in a first direction, and extending in a second direction intersect with the first direction, a first insulating layer on the active area, a charge storage layer on the first insulating layer, the charge storage layer having an upper surface with a taper shape, a second insulating layer covering the upper surface of the charge storage layer, and a control gate electrode on the second insulating layer, the control gate electrode extending in the first direction.

Nonvolatile semiconductor memory device

According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.

According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value &#x394;Erequired for charging one electron in the first conductive nanoparticle is smaller than an average energy value &#x394;E required for charging one electron in the second conductive nanoparticle, and a difference between &#x394;Eand &#x394;E is larger than a heat fluctuation energy (kT).

Nonvolatile semiconductor memory

According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other.

Nonvolatile semiconductor memory device with a narrowing charge storage layer

According to one embodiment, a nonvolatile semiconductor memory including a first gate insulating film formed on a channel region of a semiconductor substrate, a first particle layer formed in the first gate insulating film, a charge storage part formed on the first gate insulating film, a second gate insulating film which is formed on the charge storage part, a second particle layer formed in the second gate insulating film, and a gate electrode formed on the second gate insulating film. The first particle layer includes first conductive particles that satisfy Coulomb blockade conditions. The second particle layer includes second conductive particles that satisfy Coulomb blockade conditions and differs from the first conductive particles in average particle diameter.

A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.

Semiconductor device and method for manufacturing the same

In one embodiment, there is provided a semiconductor memory that includes: a semiconductor substrate having a channel region; a first tunnel insulating film on the channel region; a first fine particle layer on the first tunnel insulating film, the first fine particle layer including first conductive fine particles; a second tunnel insulating film on the first fine particle layer; a second fine particle layer on the second tunnel insulating film, the second fine particle layer including second conductive fine particles; a third tunnel insulating film on the second fine particle layer; a third fine particle layer on the third tunnel insulating film, the third fine particle layer including third conductive fine particles. A mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles and that of the third conductive fine particles.

Semiconductor memory

A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.

Random number generating device

A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Si(SiO)(SiN)M(M is an element other than Si, O, and N, x&#x2267;0, 1&#x2267;y&#x2267;0, z&#x2267;0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.

A semiconductor device includes a semiconductor region having a source region, a drain region, and a channel region provided between the source region and the drain region, a first tunnel insulation film formed on the channel region, a barrier layer formed on the first tunnel insulation film and having an energy barrier, a second tunnel insulation film formed on the barrier layer, a charge storage portion formed on the second tunnel insulation film and comprising an insulation film expressed by Si(SiO)(SiN)M(where, M denotes an element other than Si, O, and N, and 0&#x2266;X&#x2266;1, Y&#x3e;0, and Z&#x2267;0), and a control electrode formed on the charge storage portion and controlling a height of the energy barrier.

Semiconductor device

Random number generating element comprises source region, drain region, semiconductor channel provided between source region and drain region and having portion of width W and length L, width W and length L satisfying W&#x2266;(&#x3c0;/10(&#x3bc;m))/L, tunnel insulation film provided on semiconductor channel, and conductive fine particle group containing conductive fine particles provided on tunnel insulation film with surface density not less than 2.5&#xd7;10cm, charge and discharge of electrons generating between conductive fine particles and semiconductor channel via tunnel insulation film, wherein following inequalities are satisfied:(Tox=0.8 nm)]&#xd7;exp[0.3 nm&#xd7;(0.8 nm/)&#xd7;(4&#x3c0;(2&#xd7;3.1 eV))],(q/4&#x3c0;&#x2208;)&#x2266;26eV,[/()]&#xd7;[(Tox=0.8 nm)](&#x3bc;m)where Drepresents surface density, d average diameter, T thickness, Rtunnel resistance per unit area, R(Tox=0.8 nm) tunnel resistance, per unit area, of tunnel oxide film with thickness of 0.8 nm, h Plank's constant, q elemental charge, m effective mass, and &#x2208; dielectric constant.

Random number generating element

A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

Growing community of inventors

Kawasaki, Japan

Ryuji Ohba