Kabushiki Kaisha Toshiba

Ryuji Ogawa

Koji Hashimoto

Satoshi Tanaka

Toshiya Kotani

Suigen Kyoh

Kyoko Izuha

Takashi Sato

Soichi Inoue

Shigeki Nojima

Hiromitsu Mashita

Fumihiro Minami

Shimon Maeda

Toshiki Morimoto

Takafumi Taguchi

Hirotaka Ichikawa

Toshiaki Ueda

Masahiro Miyairi

A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.

Pattern generating method, method of manufacturing semiconductor device, computer program product, and pattern-shape-determination-parameter generating method

A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

Pattern data creating method, pattern data creating program, and semiconductor device manufacturing method

A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.

Pattern verification method, program thereof, and manufacturing method of semiconductor device

A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.

Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device

There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

Design layout preparing method

A flip-flop circuit includes first and second logic gates, a first selection circuit and a latch circuit. The first logic gate executes a logic operation on a first data signal and a first control signal. The second logic gate executes a logic operation on a second data signal and the first control signal. The operation results of the first and second logic gates are forcibly fixed to a predetermined value irrespective of the first and second data signals, if the first control signal is asserted. A first selection circuit selects one of the operation results of the first and second logic gates, and outputs the selected operation result as a first selection signal. A latch circuit latches the first selection signal.

Flip-flop circuit for capturing input signals in priority order

An apparatus for optical proximity correction according to an embodiment of the present invention has a data collector configured to collect source data of a circuit pattern, an edge line detector configured to detect edge lines each of which has a size that is less than a line width of the electrical circuit pattern, an edge line modifier configured to modify each of the edge lines so as to prevent an excess optical proximity correction, and a data synthesizer configured to generate pre-correction data from the modified edge lines and the source data.

Growing community of inventors

Yokohama, Japan

Ryuji Ogawa