Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Ryuji Nishikubo

Norio Aoyama

Hiroki Matsudaira

Hirokuni Yano

Jun Kano

Aurelien Nam Phong Tran

Mel Stychen Sanchez Tan

Eiji Yoshihashi

According to one embodiment, a semiconductor storage device includes a volatile memory, nonvolatile memory chips, channels, nonvolatile memory interfaces, and a bus arbiter. Each of the channels is connected to at least one nonvolatile memory chip of the nonvolatile memory chips. Each of the nonvolatile memory interfaces is connected to at least one channel of the channels and controls the at least one nonvolatile memory chip via the connected channel. The bus arbiter controls use of a bus in data transfer between the volatile memory and each of the nonvolatile memory chips in accordance with a bandwidth of the bus.

Semiconductor storage device

A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.

Storage device and method of controlling storage device

A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.

Memory system

According to one embodiment, a memory system includes a nonvolatile memory having a first writing area and a second writing area, and a controller, in which the controller confirms whether processing of preserving data which has been written before shutdown which is not going through a predetermined shutdown procedure is being executed, in the nonvolatile memory, when the controller receives a write command, causes the nonvolatile memory to write data to the first writing area if the processing is not being executed, and causes the nonvolatile memory to write data to the second writing area if the processing is being executed.

Memory system confirming whether processing of preserving data which has been before shutdown

According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.

Memory system and control method of the same

According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory.

Memory system and method of controlling memory system

A controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.

According to one embodiment, a memory system includes nonvolatile memory and storage unit storing a translation table indicating, by a predetermined management unit, relationships between logical addresses specified by a host and physical addresses in the nonvolatile memory. A memory system of the embodiment includes a controller that when receiving from the host a delete notification indicating a delete area smaller than the management unit specified by a logical address, write a specified data pattern to an area of the nonvolatile memory having a physical address corresponding to the delete area.

Memory system, controller, and method for controlling memory system

According to one embodiment, a memory system includes a non-volatile memory, a volatile memory, a controller, and a compression/decompression processor. When data transmission is performed through the volatile memory between a host apparatus and the non-volatile memory, the controller updates management information stored in the volatile memory. In addition, the compression/decompression processor compresses the management information in the case where a first condition is satisfied, and decompresses the compressed management information in the case where a second condition is satisfied. The controller stores the compressed management information in the non-volatile memory.

Growing community of inventors

Kawasaki, Japan

Ryuji Nishikubo