Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Ryuji Nishihara

Masanori Shirahama

Toshiaki Kawasaki

Masashi Agata

Yasuhiro Agata

Shinichi Sumi

Hirohito Kikukawa

Yasue Yamamoto

Hiroyuki Sadakata

Naoki Kuroda

Kazunari Takahashi

A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

System LSI

A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.

Electric fuse circuit available as one time programmable memory

The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.

Electrical fuse device

Electrical fuse blocks () of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (). The electrical fuse block () includes a program shift register block () made up of shift registers () which are disposed for the respective electrical fuse cores (), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors () of the electrical fuse cores (). When performing programming according to programming decision signal PBn, the program shift register block () transmits the program enable signal FPGI. When not performing programming, the program shift register block () skips the program enable signal FPGI.

Semiconductor storage device including electrical fuse module

An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores () each of which has an electrical fuse element () and a switch transistor () connected in series with each other, and shift registers () connected to the plurality of electrical fuse cores () to program the electrical fuse elements (). Program enable signals (Si) are sequentially generated and transferred by the shift registers (), the switch transistors () are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements () are blown one by one.

Electrical fuse circuit

A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.

Semiconductor integrated circuit

Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.

Semiconductor memory device

Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.

Semiconductor memory

A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing '0' are not selected and data is written only in a bit cell for storing '1', so that write operation performed in steps is achieved.

Nonvolatile semiconductor memory device and method for fabricating the same

A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.

Semiconductor integrated circuit device and method for testing the same

In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be 'H', the output of the differential amplifier is fixed to be 'H' and thus an output of the first bit cell is read out through gates.

A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.

Nonvolatile semiconductor memory device

A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines. Thereby, it becomes unnecessary to separately provide strapping regions at the ends of memory cell array portions and it becomes unnecessary to increase the intervals between the memory cells by increasing the size of the memory cell in the layout according to the standard CMOS process and, therefore, contacts for strapping word lines can be provided for each memory cell, without increasing the area of memory cell array portions or the chip area, so that the propagation delay of drive signals in word lines can be reduced and high speed memory operation can be implemented.

Growing community of inventors

Osaka, Japan

Ryuji Nishihara