Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Ryuji Mano

Hiromi Notani

Tsutomu Yoshimura

Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.

Voltage controlled oscillation circuit

A signal according to a phase difference in a first phase-locked loop is transferred to a power supply line as an operation power supply voltage for a first oscillation circuit included in the first phase-locked loop. The potential of the power supply line is supplied to a second oscillation circuit in a second phase-locked loop as an operation power supply voltage. The second phase-locked loop is used to generate a clock signal phase-synchronized to the input clock signal. Consequently, a clock generator is implemented that oscillates at a central frequency to generate a recovered clock signal even when a variation is caused in a manufacturing parameter.

Clock generator for generating internal clock signal synchronized with reference clock signal

The semiconductor memory device capable of performing a repair using only the fuses for programming a defective address is provided. The semiconductor memory device is provided with at least two replacement programming circuits. Each replacement programming circuit includes a programming circuit for programming a defective address. An output of each replacement programming circuit is used as a signal for indicating whether to perform or not to perform a replacement. A word line that cannot be repaired by one replacement programming circuit is repaired using an output from another replacement programming circuit.

Growing community of inventors

Hyogo, Japan

Ryuji Mano