Hitachi, Ltd.

Ryuji Kondo

Yuji Yatsuda

Shinichi Minami

Takaaki Hagiwara

Yokichi Itoh

Masatada Horiuchi

The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Semiconductor device having aligned semiconductor regions and a

Semiconductor device and method for manufacturing the same

Method for manufacturing a semiconductor device

Method for manufacturing field effect transistors

Method of forming well regions for field effect transistors utilizing

A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

Nonvolatile semiconductor memory

Method of manufacturing field-effect transistors utilizing self-aligned

An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.

Defect-remediable semiconductor integrated circuit memory and spare

A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

Nonvolatile MNOS semiconductor memory

A metal-silicon nitride-silicon oxide-substrate (MNOS) type nonvolatile memory device is disclosed. After the silicon nitride film has been formed, the heat treatment in the hydrogen atmosphere is performed. As a result of this heat treatment, the degradation of the memory retention characteristic is prevented so that a nonvolatile memory device having a silicon gate can be obtained which is comparable to a conventional nonvolatile memory device having an aluminum gate.

Growing community of inventors

Kodaira, Japan

Ryuji Kondo