Fujitsu Corporation

Ryuji Kayama

Koichi Sugama

Takashi Kaiga

Yukio Katayanagi

Masahiro Shioda

Tsutomu Chikazawa

Kenichi Yajima

Takashi Nakano

Hiroyuki Suzuki

Nobuyuki Kobayashi

Hideki Matsui

Hideo Abe

Mitsuhiro Kawaguchi

Noboru Shimizu

Akira Nozawa

Yoshihiro Onoda

Koji Suda

Toshikazu Yamakawa

A transmission system includes: a first transmission apparatus to distribute a synchronization clock; and one or more second transmission apparatuses each to connect to the first transmission apparatus so as to synchronize with the synchronization clock from the first transmission apparatus, the second transmission apparatus including: a selection portion to select the first or second transmission apparatus of a connection destination so as to switch the synchronization clock; an output portion to generate an inquiry signal addressed to the first transmission apparatus via the second transmission apparatus of the connection destination selected; a determination portion to determine whether or not the inquiry signal generated by the second transmission apparatus is received; and a second control portion to determine that there is a synchronization clock loop having a loop path through the second transmission apparatus of the connection destination when the determination portion receives the inquiry signal.

Transmission system, transmission apparatus, and clock synchronization method

A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.

Device for synchronizing between an active unit and a standby unit

A plug-in card for an optical transmission apparatus includes a J1generating unit. The J1 generating unit sends information on on-use side J1 data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 generating unit receives information on on-use side J1 data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 generating unit matches spare side J1 data to the on-use side J1 data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 generating unit does in processing B3 byte data.

Plug-in card for optical transmission apparatus

In a power supply monitoring device, a power supply voltage monitoring portion always monitors a power supply voltage supplied to a monitored circuit and outputs a voltage reduction signal when detecting that the power supply voltage is reduced below a predetermined threshold (e.g. a second voltage higher than a voltage guaranteeing a normal operation of the monitored circuit and lower than a rated voltage). A monitoring controller having received the voltage reduction signal determines whether or not an operational malfunction has occurred in the monitored circuit by comparing operation data of the monitored circuit with reference data of the monitoring controller itself. Also, the monitoring controller executes recovery processing (reset processing or reference data overwrite processing) suitable for the monitored circuit referring to a prestored recovery processing type specific to the monitored circuit when detecting an operational malfunction of the monitored circuit.

Power supply monitoring device

A traffic shaping control device for an ATM communication network which permits downscaling of hardware and eliminates a delay of cells that is caused by performing a delay process on cells which need not be subjected to the delay process. The flow rate of cells of each of connections is checked with the use of flow rate calculating unit, and a cell exceeding a predetermined reference flow rate is circulated through a delay loop, which is constituted by delay-controlled cell detecting unit, delay-passed cell detecting unit, number-of-repetitions monitoring unit and delay unit, a number of times corresponding to an initial number of repetitions determined for each connection. Such a cell is therefore delayed so that the flow rate may eventually become lower than or equal to the predetermined reference flow rate. The cell flow rate is thereafter again checked by the flow rate calculating unit, and the above operation is repeated until the flow rate is reduced to the predetermined reference flow rate or below.

Traffic shaping device for ATM communication network

Growing community of inventors

Kawasaki, Japan

Ryuji Kayama