Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Ryuji Hada

Keiri Nakanishi

Atsushi Masuda

Masato Sumiyoshi

Takashi Miyamori

Shunichi Ishiwata

Katsuyuki Kimura

Yasuki Tanabe

Takahisa Wada

Ken Tanabe

Yutaka Ota

An image processing apparatus in an embodiment includes a FIFO memory, a plurality of line buffers, an image processing circuit, and a control circuit. The plurality of line buffers store data inputted from a plurality of cameras. The image processing circuit performs predetermined image processing on the data stored in the plurality of line buffers. The control circuit performs control, according to an output control signal, such that output of data to the plurality of line buffers is stopped and the data stopped from being outputted is stored in the FIFO memory.

Image processing apparatus

An image processing apparatus according to an embodiment includes a preprocessing circuit and a distortion correction circuit configured to process, in a time division manner, a plurality of images generated by a plurality of image pickup units and an output buffer circuit configured to buffer the processed plurality of images in a unit of a block and add an identification tag including an address and an identification ID to the block.

Image processing apparatus and image processing method

According to one embodiment, an image processing device includes buffer circuitry, calculation circuitry, and control circuitry. The buffer circuitry includes n buffer circuits corresponding to each of n cameras, and stores pixel data sequentially output from each of the n cameras. The calculation circuitry reads, as line image data, a pixel data group for one line which is stored in one buffer circuit, and generates frame image data using data obtained by performing image processing on the line image data. The control circuitry stores the pixel data from a certain camera in a certain buffer circuit, and selectively sets a read destination of the pixel data as a base of the line image data to any one of the buffer circuits in which the pixel data not subjected to the image processing is stored.

Image processing device

An image processing apparatus includes first and second line buffers, an image processing circuit configured to perform an image processing on first pixel data stored in the first line buffer and then second pixel data stored in the second line buffer, and a controller configured to control writing of the second pixel data in the second line buffer at a timing aligned with a synchronizing signal and reading of the second pixel data written in the second line buffer for the image processing by the image processing circuit at a timing of a completion of the image processing by the image processing circuit of the first pixel data stored in the first line buffer.

Image processing apparatus, image processing method, and image processing program

An image processing apparatus includes an input buffer, a processor configured to convert a position of an input pixel of an input image received into the input buffer into a first pixel position of an output image using a first conversion function, convert a position of an output pixel in a vicinity of the first pixel position of the output image into a second pixel position of the input image using a second conversion function, calculate a pixel value of the second pixel position by interpolation using pixels of the input image that are in a vicinity of the second pixel position of the input image, and output the position of the output pixel as a corrected position of the input pixel and the calculated pixel value as a pixel value at the corrected position.

Image processing apparatus and distortion correction coefficient calculation method

The image processing device of an embodiment, to which multiple inputted pixels forming an inputted image are inputted in a raster scan order, includes a written pixel position calculating circuit configured to convert the position of each of the inputted pixels to a first pixel position in an outputted image, a read-out pixel position calculating circuit configured to convert the position of an outputted pixel near the first pixel position in the outputted image to a second pixel position in the inputted image, and a pixel interpolating circuit configured to calculate the pixel value of the second pixel position through interpolation with surrounding pixels in the inputted image.

Image processing device and image processing method

An image processing apparatus of an embodiment includes: a distortion correction circuit configured to perform a correction operation to a plurality of pixels composing an input image; a plurality of output buffers layered to two or more stages configured to receive an output of the distortion correction circuit, and perform output for each transmission block which is a set of pixels with the consecutive corrected pixel positions; and a controller configured to write an output pixel of the distortion correction circuit in the first-stage output buffer, sequentially transfer the written pixel to a post-stage output buffer, and cause output buffers at respective stages to store pixels of sub-blocks into which the transmission block is divided.

A light source estimating apparatus of embodiments has a sensitivity ratio spatial distribution calculating unit configured to extract a first color pixel and a second color pixel which have close spectral sensitivity and which have different sensor responses from a first picked up image picked up with an image sensor under an arbitrary light source, and calculate a ratio between a signal value of the first color pixel and a signal value of the second color pixel to acquire a first sensitivity ratio spatial distribution, and a similarity determining unit configured to estimate a type of the arbitrary light source based on similarity between a second sensitivity ratio spatial distribution group calculated using a second picked up image picked up with the image sensor under a known light source and the first sensitivity ratio spatial distribution.

Light source estimating apparatus and image pickup apparatus

A projector is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

LCOS projector having signal correction processing based on projection lens distortion

An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Image processor and command processing method

According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Compiling device and compiling method

An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Image processing apparatus and image processing system

A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

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Yokohama Kanagawa, Japan

Ryuji Hada