Kabushiki Kaisha Toshiba

Ryuichiro Ohyama

Atsushi Mizuno

Katsuya Uchida

Atsushi Masuda

Yutaka Ota

Nobuo Matsui

Kazuyoshi Kohno

Megumi Tangoda

Nobu Matsumoto

Toshiki Kizu

Yuji Ishikawa

A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.

Multi-core processor system with thread queue based power management

A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.

Program segment searching for extension instruction determination to design a processor that meets performance goal

In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.

System LSI development apparatus and the method thereof for developing a system optimal to an application

A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions

A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions.

Growing community of inventors

Tokyo, Japan

Ryuichiro Ohyama