Matsushita Electric Industrial Co., Ltd.

Ryuichi Yamaguchi

Yasuhiro Tomita

Atsushi Yamamoto

Keiichi Kurokawa

Nobufusa Iwanishi

Masaaki Hirata

Hisakazu Edamatsu

A method of accurately estimating a time delay caused by a target cell where a target supply voltage is applied to the cell. Time delays, caused by a representative cell, are represented as a function of supply voltages applied to the cell, thereby deriving an approximation function k . An interpolation function k is derived from the approximation function k by reference to two points P and P . P indicates a time delay T caused by the target cell where a supply voltage V is applied thereto, while P indicates a time delay T caused by the target cell where a different supply voltage V is applied thereto. Thus, the interpolation function k represents the time delays caused by the target cell as a function of supply voltages. And by using this interpolation function k , a time delay caused by the target cell at the target supply voltage can be estimated accurately.

Method of estimating time delay

In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.

Timing verifying method

A line capacitance is estimated in consideration of an influence of an adjacent line in rough routing, so that line paths can be determined so as to be free from a timing error. A routing graph is generated from a target integrated circuit, and line paths of cell-to-cell lines are initially determined on the basis of a passage cost set with regard to each of edges of the routing graph. With regard to each edge of the routing graph, the number of cell-to-cell lines passing through the edge is obtained as a line density, and a line capacitance of each line path in view of the influence of an adjacent line is estimated on the basis of the line density. It is verified whether or not there is a timing error with a delay time estimated, and when the integrated circuit does not satisfy a predetermined timing constraint, the line paths are re-determined with the passage cost of each edge allowed to be affected by the line capacitance. Alternatively, allocation to an interconnect layer is changed or a line-to-line distance is increased, so that the integrated circuit can satisfy the timing constraint.

Line path determining method and delay estimating method

A signal propagation time in an integrated circuit can be calculated based on a signal delay time in each of the cells composing the integrated circuit. The signal delay time in each cell can be calculated from the load capacity of a wire connected to an output terminal of the cell and from the slew of the waveform of an input signal. To calculate the slew of the waveform of the input signal, it is required to trace back the path of the input signal. When a feedback loop exists in the integrated circuit, the process of tracing back the path of the input signal may result in an endless loop. To prevent the occurrence of the endless loop, if an input terminal for a clock signal is present in a cell having an output terminal at which a signal waveform is not calculated, the signal waveform at the output terminal is calculated based on the waveform of the clock signal. In addition, a directory in which the correspondence of the output terminal and the input terminal is recorded is produced so that the signal waveform at the output terminal can be calculated based on the signal waveform at the corresponding input terminal recorded in the directory.

Method and apparatus for calculating slew rates and signal propagation

Signal propagation delay in an inverter chain having a first inverter cell and a second inverter cell connected by an intercell wire, is evaluated. In order to guarantee that a first inverter cell delay is always evaluated to be positive (A) a logic threshold voltage for an increase in input pin voltage of the first inverter cell is set to a voltage below a switching threshold voltage of the first inverter cell, and (B) a logic threshold voltage for a decrease in input pin voltage of the first inverter cell is set to a voltage above the switching threshold voltage of the first inverter cell. Similarly, logic threshold voltages for an increase and a decrease in input pin voltage of the second inverter cell are determined. Additionally, in order to guarantee that an intercell wire delay is always evaluated to be positive, logic threshold voltages for an output pin voltage of the first inverter cell are made to agree with the logic threshold voltages for the input pin voltage of the second inverter cell.

Method of evaluating signal propagation delay in logic integrated circuit

After limited in band area with a vertical or horizontal low-pass filter in a sub-sampling circuit at the image-signal transmitting side, an image signal is sub-sampled as inter-frame offset in the form of a quincunx, and then transmitted to an image-signal receiving side through a transmission system. The sampling rate of the image signal thus received is converted by a sampling rate conversion portion. According to the operation of a changeover switch by the operator who watches a Braun tube for image reproduction, a selector selects the image signal interpolated with a vertical filter of a low-pass portion when the sub-sampling circuit uses a vertical filter, or the image signal interpolated with both vertical and horizontal low-pass filters when the sub-sampling circuit uses a two dimensional filter. Thus, there is supplied an image signal which has been interpolated with a low-pass filter of which transmissible band area is identical with or approximate to that of the low-pass filter in the sub-sampling circuit at the signal transmitting side, such that the image signal contains no aliasing interference of a spatial frequency band area. Thus, there can be reproduced a good picture in which a horizontal straight line is not displayed as a broken line.

Circuit for executing an interpolation processing on a sub-sampled image

A physical memory allocation system comprising an area estimation section, a program modification section, a program size read-in section, a memory size read-in section, a user control table, a size compare section, and an area allocation section. The area estimation section, after a program has been run for a predetermined period of time, measures a memory area size referred to by the program (i.e. the program size). The program modification section writes the program size to the program. The program size read-in section inputs the program size and the memory size read-in section inputs a user allocation size held at the user control table at program execution time. The size compare section makes a comparison in size between the user allocation size and the program size thereby outputting one of these two sizes that is found to be smaller than the other as an at-execution-time size. In the area allocation section, an amount of physical memory that a program can use is taken as an at-execution-time size. Taking such a physical memory size as a low limit, physical memory allocation is carried out effectively. This reduces the frequency of swapping and the loss of time.

Physical memory allocation system, program execution scheduling system,

In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.

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Osaka, Japan

Ryuichi Yamaguchi