Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Ryuichi Sahara

Nozomi Shimoishizaka

Yoshifumi Nakamura

Kazumi Watase

Hiroaki Fujimoto

Takahiro Kumakawa

Kazuyuki Kaino

Keiji Miki

Masanori Minamio

Toshiyuki Fukuda

Toru Nomura

Yutaka Harada

Yasutake Yaguchi

Shinji Murakami

Kazuyuki Kainou

Kazuyuki Kainoh

Kenichi Itou

There are provided a lead frame including a plurality of first external terminal portionsprovided on a plane, inner lead portionsformed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portionsformed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor elementflip-chip bonded to the inner lead portions via bumps; and an encapsulating resinencapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. A plurality of terminalsfor electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin. A plurality of semiconductor elements or coils and resistors can be incorporated, and further semiconductor devices can be stacked.

Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same

A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.

Method for fabricating a chip-scale-packaging (CSP) having an inductor

The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.

Semiconductor device including a diffusion layer

Disclosed is a semiconductor devicecomprising a first semiconductor elementwith an arrangement of first element electrodes, a second semiconductor elementwith an arrangement of second element electrodes, a connection memberelectrically connecting together a portionof the first element electrodesand the second element electrodes, an insulation layercovering a major surfaceof the first semiconductor elementand a backside surfaceof the second semiconductor element, a wiring layerformed on the insulation layerand electrically connected to the first element electrode portionexposed in an opening portion, and an external electrodeformed, as a portion of the wiring layer, on the insulation layer

Semiconductor device and method for the fabrication thereof

Semiconductor device having an inductor formed on a region of an insulating film

A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.

Semiconductor device and method for producing the same

A low elasticity layer ( ) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate ( ). On the low elasticity layer ( ), lands ( ) serving as external electrodes are disposed, and pads ( ) on the element electrodes, the lands ( ) and metal wires ( ) for connecting them are integrally formed as a metal wiring pattern ( ). A solder resist film ( ) having an opening for exposing a part of each land ( ) is formed, and a metal ball ( ) is provided on the land ( ) in the opening. The low elasticity layer ( ) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires ( ).

Semiconductor device and method for manufacturing the same

Semiconductor device including a diffusion layer formed between electrode portions

A semiconductor device includes a semiconductor chip, an insulating layer formed on a region excluding the plurality of electrode pads on the principal surface of the semiconductor chip, a plurality of contact pads arranged on the insulating layer, a wiring layer electrically connected to at least one of the plurality of electrode pads and electrically connected to at least one of the plurality of contact pads, thereby establishing rewiring connection, an insulative resin layer formed on a region excluding the plurality of contact pads on the principal surface of the semiconductor chip, a protruded electrode provided on each of the plurality of contact pads, and an underfill material layer provided on the insulative resin layer in such a manner that the top of the protruded electrode is exposed.

Semiconductor device and method for producing the same, and method for mounting semiconductor device

A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; a resin encapsulant; and a mark member. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. The mark member is embedded in the upper surface of the resin encapsulant. The mark member, which is transferred from a transfer sheet in a single process step, is highly visible and can be formed efficiently.

Method of embedding an identifying mark on the resin surface of an encapsulated semiconductor package

A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; and a resin encapsulant. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate and a second bottom face of the semiconductor chip is in contact with the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. A level difference exists between a first bottom face and the second bottom face of the semiconductor chip. The first and second bottom faces are respectively located at a peripheral portion and a central portion of the semiconductor chip. A part of the resin encapsulant is interposed between the first bottom face and the upper surface of the wiring substrate. Thus, the resin encapsulant and the semiconductor chip are secured more strongly to each other, and so are the resin encapsulant and the wiring substrate.

Semiconductor device and method for fabricating the same

Disclosed is a semiconductor device comprising a first semiconductor element with an arrangement of first element electrodes , a second semiconductor element with an arrangement of second element electrodes , a connection member electrically connecting together a portion of the first element electrodes and the second element electrodes , an insulation layer covering a major surface of the first semiconductor element and a backside surface of the second semiconductor element , a wiring layer formed on the insulation layer and electrically connected to the first element electrode portion exposed in an opening portion , and an external electrode formed, as a portion of the wiring layer , on the insulation layer

A low elasticity layer (,) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (,). On the low elasticity layer (,), lands (,) serving as external electrodes are disposed, and pads (,) on the element electrodes, the lands (,) and metal wires (,) for connecting them are integrally formed as a metal wiring pattern (,). A solder resist film (,) having an opening for exposing a part of each land (,) is formed, and a metal ball (,) is provided on the land (,) in the opening. The low elasticity layer (,) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (,).

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Osaka, Japan

Ryuichi Sahara