Nec Corporation

Taiyo Yuden Co., Ltd.

Taiyo Yudenco., Ltd.

Ryuichi Okamura

Shinji Taniguchi

Tsuyoshi Yokoyama

Hiroshi Kawakami

Hiroomi Kaneko

Yoshiyuki Yagami

Yoshiaki Takaoka

A piezoelectric thin film resonator includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; and a wiring layer located on the upper electrode, the wiring layer having a thickness equal to or greater than 0.8 &#x3bc;m and equal to or less than 3.0 &#x3bc;m, at least a part of the wiring layer overlapping in plan view with a resonance region in which the lower electrode and the upper electrode face each other across the piezoelectric film, a distance between an outline of the resonance region and an edge of a lower surface located within the resonance region and farthest from the outline being greater than 0 &#x3bc;m and less than 2 &#x3bc;m.

Piezoelectric thin film resonator, filter, and multiplexer

A piezoelectric thin film resonator includes: a lower electrode and an upper electrode facing each other across a piezoelectric film; an insertion film inserted into the piezoelectric film, located in at least a part of an outer peripheral region in a resonance region and outside the outer peripheral region, and not located in a center region of the resonance region; a protective film on the upper electrode and the piezoelectric film; and a wiring line connecting to the lower electrode and covering an outer periphery of the protective film in an extraction region of the lower electrode, wherein in the extraction region, an outer periphery of the insertion film is further out than an outer periphery of the upper electrode and further in than an outer periphery of the piezoelectric film, and the outer periphery of the protective film is further out than the outer periphery of the insertion film.

Piezoelectric thin film resonator and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a wiring formed on the semiconductor substrate, a cover film formed on the semiconductor substrate and the wiring. The cover film has a through hole to expose the wiring. A pad is formed in the through hole to electrically connect to the wiring without being formed on a top surface of the cover film.

Semiconductor device having improved pad coupled to wiring on semiconductor substrate

A semiconductor device has at least a p-channel MOS field effect transistor and at least an n-channel MOS field effect transistor, both of which are integrated on a single semiconductor substrate. The p-channel MOS field effect transistor has at least a first p-type lightly doped diffusion region adjacent to a p-type drain diffusion region. The n-channel MOS field effect transistor has at least a first n-type lightly doped diffusion region adjacent to an n-type drain diffusion region. The first p-type lightly doped diffusion region of the p-channel MOS field effect transistor is shorter in a direction parallel to a channel length direction than a first n-type lightly doped diffusion region of the n-channel MOS field effect transistor.

Method of forming CMOS device with improved lightly doped drain structure

The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region. The diffusion capacitance reduction layer may be doped with an impurity of the second conductivity type at a third impurity concentration which is at least lower than the second impurity concentration of the semiconductor bulk region and not lower than zero or may be mode of an insulating material to thereby reduce a capacitance of the diffusion region.

Field effect transistor with improved source/drain diffusion regions

By assuming a symbol A for the contact depth, B for the diameter of the contact, C for the thickness of the underlay oxide to be formed between the barrier film and the semiconductor substrate, and D for the eave protrusion length of the barrier film the eaves being formed inside the contact when oxide wet etching is performed for removing natural oxide on the silicon and for reducing the contact resistance, the following relation is established,

Semiconductor device having a barrier film for preventing penetration of

A semiconductor device includes a silicon substrate, a first insulating film, a barrier film, a contact hole, a protective film, a barrier metal, and an interconnection metal. A semiconductor element is formed on the silicon substrate. The first insulating film is formed on the silicon substrate. The barrier film is formed on the first insulating film to prevent moisture from externally entering. The contact hole is formed through the barrier film and the insulating film to a depth at which the silicon substrate is exposed. The protective film is formed on the side surface of the contact hole to protect the first insulating film against etching which is performed to remove a spontaneous oxide film formed on a surface of the silicon substrate which is exposed on a bottom surface of the contact hole. The barrier metal is continuously formed on at least the side and bottom surfaces of the contact hole and serves as a buffer conductor. The interconnection metal is buried in the contact hole on which the barrier metal is formed. A semiconductor device manufacturing method is also disclosed.

Growing community of inventors

Tokyo, Japan

Ryuichi Okamura