Mitsubishi Denki Kabushiki Kaisha

Ryuichi Kosugi

Shigeki Ohbayashi

Nobuhiro Tsuda

Ryuichi Matsuo

Osamu Ishizaki

Tsugio Tabaru

A silicon wafer has a plurality of chip portions and a plurality of street portions. Each of the street portions runs and spaces between neighboring chip portions. The wafer also has circuits each provided on the street portions. The circuit is reinforced by a reinforcing portion. The reinforcing portion is provided on the circuit before dicing and then cut out in part by dicing so that it remains in part on at least one end portion of the circuit, adjacent to the chip portions, after dicing.

Semiconductor chip and its manufacturing method

A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate, an etching stopper, an interlayer insulating film having a contact hole and having an etching rate greater than that of the etching stopper, a high concentration impurity region formed by implanting an impurity into the silicon substrate through the contact hole, a plug layer filling the contact hole, and an interconnection layer.

Semiconductor device and method of manufacturing the same

A synchronous semiconductor memory device according to the present invention includes a memory array circuit for performing reading/writing of data sent to or received at a data terminal with respect to a memory cell array; a write data retaining circuit and a write address retaining circuit for temporarily retaining write data and addresses corresponding to the write data, respectively; an address matching circuit for performing matching of an input address with addresses stored in the address retaining circuit; and a data path select circuit for outputting the write data temporarily stored in the write data retaining circuit to the data terminal according to the matching result. The address matching circuit is disabled during a clock cycle in which a writing operation is designated.

Semiconductor memory device employing pipeline operation with reduced power consumption

A synchronous semiconductor memory device includes a clock pulse generator generating internal first and second clock pulses in synchronization with an external clock signal for application, respectively, to a word line select decoder selecting a row of memory cells, and to a bit line select decoder selecting a column of memory cells, a sense amplifier sensing and amplifying a data of selected memory cell and a write driver writing a data to the selected memory cell. Word line select decoder is enabled when the first clock pulse is active, and bit line select decoder, sense amplifier and write driver are activated when the second clock pulse is active. These circuits are activated only for a necessary minimum period, and current consumption is reduced.

Clock synchronous semiconductor memory device having current consumption

A semiconductor memory device includes an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of the memory cells; a plurality of bit lines connected to the columns of the memory cells; word line selection means; bit line selection means; and equalizing means for equalizing the bit line to a desired voltage level in response to an address signal, and for terminating the equalization in response to change in a signal on a word line according to change in the address signal.

Semiconductor memory device having equalization terminated in direct

A semiconductor pseudo memory module includes a multilayer wiring substrate on the surface of which a plurality of DRAMs are provided and on the reverse side of which semiconductor devices of the DRAM controller and multiplexers are provided, these devices being electrically connectetd with one another by a wiring layer. The address signals supplied from outside are converted into column address signals and row address signals by the multiplexer so as to be supplied to each DRAM. Responsive to control signals supplied from outside, the DRAM controller generates a refresh signals for refreshing the DRAMS, which signal is supplied to the DRAM. In this manner, the DRAM may be used as the SRAM.

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Hyogo, Japan

Ryuichi Kosugi