Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Taniguchi, Atsuki

Kondo, Ryuichi

Ohtsuka, Tomoyuki

Naitou, Hidetoshi

Ryuichi Kondo

Haruo Yamashita

Toshiyuki Sudo

Tomohiro Ishihara

Takaaki Wakisaka

Atsuki Taniguchi

Tomohiro Shinomiya

Tomoyuki Ohtsuka

Toshifumi Fujimoto

Koya Sakurai

Hidetoshi Naitou

Keiichi Kanno

A switching unit of a cross connecting device is expanded with no momentary interruption, while data loss and data overlapping is eliminated. To achieve such an expansion, a cross connecting device comprises a base set having a switching unit for determining an output channel based on virtual path information for cell data that is input and for outputting the cell data. An expanded set has a switching unit for receiving the cell data from the base set and cell data from another base set, and for determining an output channel based on virtual path information for both inputs of cell data and for outputting the cell data. A filter prevents the transmission, to the expanded set, of cell data for which the output channel is determined by the switching unit of the base set.

Uninterrupted-service expansion system for a cross connecting device

According to the present invention, when a current system is switched to a spare system in a transmission system in an asynchronous transfer mode, empty cells transmitted in the current and spare systems are detected, and thereby a timing for switching the current system to the spare system is determined. When no phase difference is existent between the current and spare systems, an empty cell is detected in both the current and spare systems at the same time. Therefore, the current system is switched to the spare system, when an empty cell is detected in both the current and spare systems at the same time. When a shade difference is existent, if an empty cell is detected either in the current or spare systems, another empty cell is inserted in to the systems. Then, the data of the empty cell in a spare system is saved. After the empty cell in a current system passes, the current system is switched to the spare system. When a phase difference of at least one cell is existent, and if an empty cell comes earlier in current system, empty cell are kept inserted form when the empty cell is detected in the current system until an empty cell is detected in the spare system. After that, the current system is switched to the spare system. When an empty cell comes earlier in a spare system, the data of the cell in the spare system is saved from when the empty cell is detected until an empty cell is detected in the current system. After that, the current system is switched to the spare system.

Apparatus and method for non-stop switching in asynchronous transfer mode

When input signals from a plurality of input ports are selected and are inserted into the time slots to be output from a single output port and to insert respective signal data into time slots in synchronization with a synchronizing signal, the apparatus is so constructed that selector units (5-i) are provided to correspond to input ports (1-i), and a synchronizing signal generating unit (4) is provided to output, synchronously, a synchronizing signal and selecting signal information for designating a selector unit (5-i); the selector unit (5-i) being provided with a determining unit (6) for determining whether or not the selecting signal information designates the selector.

Input-output signal control apparatus

A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse signal being synchronized with the beginning of the information part.

Synchronization circuit for establishing frame synchronism using

Disclosed is a drop/insert processing circuit connected to, for example, a broadband subscriber network including a high speed data loop. The circuit is formed in one body comprising a single shift register, a single clock signal generator, a low speed data insertion control circuit, and a low speed data dropping circuit, whereby the circuit scale is reduced and the control is simplified.

Drop/insert processing circuit

Growing community of inventors

Kawasaki, Japan

Ryuichi Kondo