Kawasaki Microelectronics, Inc.

Kawasaki Steel Corporation

Ryuichi Hata

Naoki Kanazawa

Masato Yoneda

Hiroshi Sasama

Masahiro Konishi

Tomoo Tsuda

Hideaki Iwasaki

A content addressable memory having a function for extending a data width to a plurality of words includes an entry configuration set unit which sets the number of words to form one entry, and a logical-segment-to-physical-segment converting circuit for converting the logical segments in one entry to the physical segments according to the setting of the entry configuration. The content addressable memory further includes a word circuit chain having the maximum number of one-word circuits belonging to each physical block which are combined to form one entry. The one-word circuits have CAM words associated therewith, and are connected in series over the physical block. A group of the words at the same number in entries where one entry is composed of a plurality of words forms a logical segment. The thus constructed content addressable memory is capable of an AND search for the words of which the addresses are apart from each other in one entry, or allows the words within one entry to be searched in an arbitrary order. Furthermore, a search operation for a portion of the words in one entry is used to do a match search for the entry. In addition, unintended word search is prevented, thereby reducing the power consumption.

Content addressable memory having data width extension capability

A signal detection circuit detects the presence or absence of signals having the same logic in a plurality of arranged signal lines, can be used as a circuit suitable for multi-hit detection in a content addressable memory. The signal detection circuit includes a first signal transmission line to transmit a first signal indicating the presence of two or more logical signals to be detected and a second signal transmission line to transmit a second signal indicating the presence of one or more of the logic signals to be detected. Each of the first and second signal transmission lines includes logic circuits. The signal detection circuit may have a hierarchical structure.

Signal detection circuit for detecting multiple match in arranged signal lines

A CAM (content addressable memory) device capable of flexibly coping with a wide range of user requirements with respect to operation speed and/or power consumption has operation mode setting means, generates a higher or lower internal voltage than an external power-supply voltage depending on the setting, and at least part of the internal circuit is operated by the internal voltage. In particular, the high level of the search-bit line and/or the high level of the match line are preferably set to the internal voltage. Also, the CAM device has bit line amplitude adjusting means for adjusting the amplitude of the bit line depending on the setting of the operation mode setting means and/or match line amplitude adjusting means for adjusting the amplitude of match line on which a search result is output, and thus is capable of appropriately changing the operation speed and power consumption depending on the setting.

Content addressable memory device having an operation mode setting means

A content addressable memory (CAM) device according to the present invention is configured with binary CAM cells capable of holding binary data &ldquo;0&rdquo; and &ldquo;1&rdquo;, and is capable of being used either as a binary CAM device with the binary CAM cells being used as binary CAM cells or as a ternary CAM device with the binary CAM cells being used as ternary CAM cells capable of holding ternary data in a way in which, in each pair of two bits of the binary CAM cells, three states, &ldquo;0,&rdquo; &ldquo;1,&rdquo; and &ldquo;X (don't care)&rdquo; are assigned to four states, &ldquo;00,&rdquo; &ldquo;01,&rdquo; &ldquo;10,&rdquo; and &ldquo;11,&rdquo; expressed by two-bit data stored in the pair. A CAM device according to the present invention is provided with a CAM array including a plurality of CAM words each formed of binary CAM cells; and a binary/ternary setting section for making a setting of a case in which the binary CAM cells are used as binary CAM cells or a setting of a case in which each pair of two bits of the binary CAM cells is used as a ternary cell.

Content addressable memory device capable of being used as binary CAM device or as ternary CAM device and structure method therefor

A ternary content addressable memory device is disclosed which writes data into a data cell and writes mask data into a mask data cell in a ternary CAM cell unit by a single write cycle when the ternary content addressable memory device is used as a binary content addressable memory device. The content addressable memory device includes at least the ternary content addressable memory cell unit which stores ternary data representing three states of &ldquo;0&rdquo;, &ldquo;1&rdquo;, and &ldquo;don't care&rdquo;. The ternary content addressable memory cell unit include the data cell for storing binary data of &ldquo;0&rdquo; and &ldquo;1&rdquo;, and the mask cell for storing mask data for masking the binary data from a searching operation. The content addressable memory device includes a write circuit which writes the binary data into the data cell while writing the mask data in an unmask state into the mask cell at the same time, when the binary data is written into the ternary content addressable memory cell unit.

Ternary content addressable memory with data and mask data settable therewithin by one write cycle

In a content addressable memory (CAM), a spare CAM word serving as a redundant circuit is mounted in addition to a plurality of CAM words, and a storage section for holding information indicating whether there is a defective CAM word in the plurality of CAM words, and if there is one or more defective CAM word, address information of the defective CAM word. Control is applied according to the address information of the defective CAM word such that the defective CAM word is replaced with the spare CAM word. The search output of the defective CAM word is replaced with that of the spare CAM word. The spare CAM word serving as a redundant circuit is mounted without increasing a circuit scale and an output delay time, and a produce yield is improved.

Content addressable memory having redundant circuit

A content addressable memory device includes a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, and a first unit for realizing a smaller swing in the level of the search bit line pair by setting the potential of the search bit line pair to an intermediate potential between a power source potential and a ground potential during match searching, and/or a second unit for realizing a smaller swing in the level of a match line by setting a precharge level of the match line to the intermediate potential between the power source potential and the ground potential.

Content addressable memory with potentials of search bit line and/or match line set as intermediate potential between power source potential and ground potential

An associative memory device in which a coincident output is held by each word and aging for word data can be efficiently performed such that the word data is made valid or invalid on the basis of the information. The associative memory device includes a plurality of words for storing data, for detecting the coincidence/non-coincidence between the data stored in the plurality of respective words and input search data. Each word further includes a memory for storing a coincidence line output by a searching operation, a storage memory for storing data representing whether the corresponding word is subjected to a searching operation or is available to write new data therein, a circuit for simultaneously setting/resetting the contents of the storage memory, and circuit for resetting/setting the memory for storing the coincidence line output by the storage memory.

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Chiba, Japan

Ryuichi Hata