Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Ryu Makabe

Masaki Tsukude

Hirotoshi Sato

Isao Nojiri

Yuichi Kunori

Shinichi Kobayashi

Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.

Semiconductor memory device

The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space is designed considering a thickness of a cutting edge of a blade and relative positioning error, and the blade does not cross any metal wirings when the blade passes through the dicing area, thereby preventing the generation of an abruption or a burr due to the dicing to enhance a yield in IC production.

Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer

A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Semiconductor device and its wiring method

Semiconductor device and its writing method

A semiconductor memory includes a first decoder selecting any of modes -n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes -n of the test mode B according to fifth to eighth data signals. When a predetermined mode m&plus;1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m&plus;1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.

Semiconductor device with test mode

When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

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Tokyo, Japan

Ryu Makabe